CS-Audio: A 16 pJ/b 0.1–15 Mbps Compressive Sensing IC With DWT Sparsifier for Audio-AR

K, Gaurav Kumar; Chatterjee, Baibhab; Sen, Shreyas

doi:10.1109/jssc.2022.3155366

Cited by 9 publications

(5 citation statements)

References 35 publications

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“…Another, more general technique (66) exploits online sensory data statistics for dynamic reconfiguration (in terms of compression algorithm, compression harshness, and sampling frequency). Recent publications (9,62,63) have demonstrated a fully digital CS subsystem equipped with an on-chip, two-stage sparsifier and a dual varying-seed pseudorandom bit sequence sensing-matrix generator, with a variable compression factor ranging from 5 to 33.33. The twostage discrete wavelet transform-based sparsifier ensures that the CS module works effectively for both sparse and nonsparse signals.…”

Section: Compressive Sensingmentioning

confidence: 99%

Bioelectronic Sensor Nodes for the Internet of Bodies

Chatterjee

Mohseni

Sen

2023

Annu. Rev. Biomed. Eng.

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Energy-efficient sensing with physically secure communication for biosensors on, around, and within the human body is a major area of research for the development of low-cost health care devices, enabling continuous monitoring and/or secure perpetual operation. When used as a network of nodes, these devices form the Internet of Bodies, which poses challenges including stringent resource constraints, simultaneous sensing and communication, and security vulnerabilities. Another major challenge is to find an efficient on-body energy-harvesting method to support the sensing, communication, and security submodules. Due to limitations in the amount of energy harvested, we require a reduction in energy consumed per unit information, making the use of in-sensor analytics and processing imperative. In this article, we review the challenges and opportunities of low-power sensing, processing, and communication with possible powering modalities for future biosensor nodes. Specifically, we analyze, compare, and contrast ( a) different sensing mechanisms such as voltage/current domain versus time domain, ( b) low-power, secure communication modalities including wireless techniques and human body communication, and ( c) different powering techniques for wearable devices and implants. Expected final online publication date for the Annual Review of Biomedical Engineering, Volume 25 is June 2023. Please see http://www.annualreviews.org/page/journal/pubdates for revised estimates.

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Section: Compressive Sensingmentioning

confidence: 99%

Bioelectronic Sensor Nodes for the Internet of Bodies

Chatterjee

Mohseni

Sen

2023

Annu. Rev. Biomed. Eng.

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“…In recent years, the development of systems that enable always-on continuous electrocardiogram (ECG) analysis and cardiac arrhythmia detection has gained significant attention. The literature documents various methods for automated arrhythmia detection [4,5], encompassing signal processing techniques like frequency analysis [6,7], wavelet transform [8,9], statistical and heuristic approaches [10,11], and machine learning models such as support vector machines [12][13][14] and artificial neural networks [15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient ECG Processor Based on HDWT and a Hybrid Classifier for Arrhythmia Detection

Deng,

Ma,

Yang

et al. 2023

Applied Sciences

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Cardiac arrhythmia (CA) is a severe cardiac disorder that results in a significant number of fatalities worldwide each year. Conventional electrocardiography (ECG) devices are often unable to detect arrhythmia symptoms during patients’ hospital visits due to their intermittent nature. This paper presents a wearable ECG processor for cardiac arrhythmia (CA) detection. The processor utilizes a Hilbert transform-based R-peak detection engine for R-peak detection, a Haar discrete wavelet transform (HDWT) unit for feature extraction, and a Hybrid ECG classifier that combines linear methods and Non-Linear Support Vector Machines (NLSVM) classifiers to distinguish between normal and abnormal heartbeats. The processor is fabricated by the CMOS 110 nm process with an area of 1.34 mm2 and validated with the MIT_BIH Database. The whole design consumes 4.08 μW with an average classification accuracy of 97.34%.

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“…Nasimi et al [10] proposed a CS method to remove redundancy completely from frames by using the pseudo-periodic nature of ECG signals, and the technique could achieve superior reconstruction quality. Kumar et al [11] showed a CS-based compression realized in a pipelined architecture, and the CS design could achieve high data rates and enable a wake-up implementation to bypass computation for insignificant input samples. Li et al [12] adopted a Compressed Learning algorithm combined with a one-dimensional Convolutional Neural Network that could directly learn ECG signals in the compression domain without expanded normalization.…”

Section: Introductionmentioning

confidence: 99%

“…However, the clock frequency of the sequence generator must be equal to that of the matrix sequence, leading to relatively high dynamic power consumption. Moreover, the conventional measurement matrix generator and its corresponding compression are in parallel [11]. A large number of matrix multiplication units make the circuit area quite large.…”

Section: Introductionmentioning

confidence: 99%

An Improved Measurement Matrix Generator for Compressed Sensing of ECG Signals

Zhao

Guo

et al. 2022

Electronics

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Compressed sensing (CS) is being widely used to compress and reconstruct data for processing electrocardiogram (ECG) signals obtained through Wireless Body Area Networks. However, the conventional measurement matrix generator and compression computations for CS are in parallel, resulting in significant power consumption and a large area. This paper proposes a serial measurement matrix generator, which reduces the clock frequencies by using linear feedback shift registers and latches. A CS circuit for ECG signals processing based on the proposed measurement matrix generator is proposed and implemented in a SMIC 55 nm CMOS process. The experimental results show that the power consumption is only 1.690 μW at 1.2 V, and the chip area is 0.608 mm2, which has obvious advantages over the traditional parallel architecture. The reconstruction results show that the Percentage Root-mean-square Difference is 1.32%, which means that the design meets the basic clinical requirements.

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CS-Audio: A 16 pJ/b 0.1–15 Mbps Compressive Sensing IC With DWT Sparsifier for Audio-AR

Cited by 9 publications

References 35 publications

Bioelectronic Sensor Nodes for the Internet of Bodies

Bioelectronic Sensor Nodes for the Internet of Bodies

An Energy-Efficient ECG Processor Based on HDWT and a Hybrid Classifier for Arrhythmia Detection

An Improved Measurement Matrix Generator for Compressed Sensing of ECG Signals

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