2020
DOI: 10.1504/ijics.2020.105185
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CSL: FPGA implementation of lightweight block cipher for power-constrained devices

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Cited by 6 publications
(2 citation statements)
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“…The tool was executed for more than 48 hours on ASUS X53S Laptop powered with Intel Core i5 2430 M processor with a clock speed of 2.40 GHz (Turbo-Boost to 3.1 GHz)28 [32], but it was unable to break 1 round of Feistel function of CSL algorithm. Therefore, our CSL algorithm avoids a brute force attack for a rational period [9].…”
Section: Brute Force Attackmentioning
confidence: 99%
See 1 more Smart Citation
“…The tool was executed for more than 48 hours on ASUS X53S Laptop powered with Intel Core i5 2430 M processor with a clock speed of 2.40 GHz (Turbo-Boost to 3.1 GHz)28 [32], but it was unable to break 1 round of Feistel function of CSL algorithm. Therefore, our CSL algorithm avoids a brute force attack for a rational period [9].…”
Section: Brute Force Attackmentioning
confidence: 99%
“…Since individual audits of these can task can be repetitive and inefficient, the TPA would naturally be able to efficiently conduct multiple auditing tasks at the same time. To address these problems, our work utilizes the technique of symmetric key encryption scheme CSL algorithm along with ultra-lightweight and fastest hashing function BLAKE3, It allows TPA to carry out the auditing without required local data copy and thus reduces coordination and overhead compared with direct approaches to data auditing [8,9]. By integrating the compressed data using LZ4 compression scheme and hashing function with a nonce, makes our proposed system works at high speed further ensuring The TPA did not know about the data content stored on the cloud server during the efficient auditing process.…”
Section: Introductionmentioning
confidence: 99%