Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration

Cheng, Yi; Lin, Bing-Hong; Lee, S.Y.; Chiu, Catherine; Wu, King‐Jean

doi:10.1109/relphy.2007.369881

Cited by 13 publications

(19 citation statements)

References 8 publications

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“…2, one can also see that for the single via Cu structure used in this work, the wide metal has longer MTF as compared with the narrow metal, in agreement with previous report [6]. This is expected since a larger void size is needed to cause metal trench To study the line width dependence of the reservoir length effectiveness in improving interconnect EM lifetime, we examine the enhancement of t 50 due to the reservoir length for structures with different line widths.…”

Section: Resultssupporting

confidence: 87%

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Width dependence of the effectiveness of reservoir length in improving electromigration for Cu/Low-k interconnects

Tan

et al. 2010

Microelectronics Reliability

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Section: Resultssupporting

confidence: 87%

“…Thus, the experimental data allows us to study the reservoir effect of this upstream EM test. In fact, this is the reason why only upstream EM test is conducted in this work since downstream EM failure location does not occur in the reservoir region as shown in the literature [6].…”

Section: Resultsmentioning

confidence: 99%

Width dependence of the effectiveness of reservoir length in improving electromigration for Cu/Low-k interconnects

Tan

et al. 2010

Microelectronics Reliability

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“…However, as metal length increased, larger width improved MTF. Cheng et al [75] also checked the dependence of MTF on line width (0.1 µm and up to 5 µm). They found for multiple via structures and narrow line widths, for example, a bamboo-like grain line; the contribution of the grain boundary diffusion was negligible because of the absence of a continuous grain boundary path.…”

Section: Setting-up Design Guidelines For Metal Width On the Basis Ofmentioning

confidence: 99%

“…Overall analysis of width and length effects, using the data from [73][74][75][76], provides the complex dependence for EM MTF (Figure 20): short L resulted in long MTF, irrespective of width. Longer L had shorter MTF due to stronger EM conditions, and a stronger dependence on width.…”

Section: Setting-up Design Guidelines For Metal Width On the Basis Ofmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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“…1) [4] to characterize both metal and via EM failure modes and for lifetime projection. Downstream and upstream test structures involve downdirectional and up-directional electron flow at the cathode via, respectively [5,6]. From EM failure consideration, via void (void inside via) or trench void (void in the metal stripe) dominate the failure mode in upstream structure [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Study of a new electromigration failure mechanism by novel test structure

Chen

Lin

Hsieh

et al. 2015

2015 IEEE International Reliability Physics Symposium

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A novel electromigration (EM) structure is designed and characterized with advanced Cu/low-k technology. Comparing the EM results derived from novel and traditional test structures, a new EM failure mechanism is proposed. The new mechanism is caused by the Cu/barrier interface damage at the metal line-edge during upper Via opening process. This damage provides a fast diffusion path. From the downstream EM test, it is observed that the thicker Ta-based ALD barrier has a higher activation energy and median time to failure compared to thinner Ta based barrier. Thicker barrier process enhances Cu/barrier adhesion and hence prevent the via opening induced interface damage.

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Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration

Cited by 13 publications

References 8 publications

Width dependence of the effectiveness of reservoir length in improving electromigration for Cu/Low-k interconnects

Width dependence of the effectiveness of reservoir length in improving electromigration for Cu/Low-k interconnects

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Study of a new electromigration failure mechanism by novel test structure

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