Cu Protrusion of Different through-Silicon via Shapes under Annealing Process

Majd, Alireza Eslami; Jeong, Il Ho; Jung, Jae Pil; Ekere, N.N.

doi:10.1007/s11665-021-05775-4

Cited by 19 publications

(7 citation statements)

References 29 publications

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“…Several properties of Cu and Si used in this study were detailed in Table 1 (Eslami Majd et al. , 2021; Jeong et al.…”

Section: Numerical Analysismentioning

confidence: 99%

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A numerical study on thermal deformation of through silicon via with electroplating defect

Hou,

Qiu,

Zhao

et al. 2024

MMMS

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PurposeBy investigating the thermal-mechanical interaction between the through silicon via (TSV) and the Cu pad, this study aimed to determine the effect of electroplating defects on the upper surface protrusion and internal stress distribution of the TSV at various temperatures and to provide guidelines for the positioning of TSVs and the optimization of the electroplating process.Design/methodology/approachA simplified model that consisted of a TSV (100 µm in diameter and 300 µm in height), a covering Cu pad (2 µm thick) and an internal drop-like electroplating defect (which had various dimensions and locations) was developed. The surface overall deformation and stress distribution of these models under various thermal conditions were analyzed and compared.FindingsThe Cu pad could barely suppress the upper surface protrusion of the TSV if the temperature was below 250 ?. Interfacial delamination started at the collar of the TSV at about 250 ? and became increasingly pronounced at higher temperatures. The electroplating defect constantly experienced the highest level of strain and stress during the temperature increase, despite its geometry or location. But as its radius expanded or its distance to the upper surface increased, the overall deformation of the upper surface and the stress concentration at the collar of the TSV showed a downward trend.Originality/valuePrevious studies have not examined the influence of the electroplating void on the thermal behavior of the TSV. However, with the proposed methodology, the strain and stress distribution of the TSV under different conditions in terms of temperature, dimension and location of the electroplating void were thoroughly investigated, which might be beneficial to the positioning of TSVs and the optimization of the electroplating process.

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“…Several properties of Cu and Si used in this study were detailed in Table 1 (Eslami Majd et al. , 2021; Jeong et al.…”

Section: Numerical Analysismentioning

confidence: 99%

“…(Eslami Majd et al, 2021;Jeong et al, 2020;Jing et al, 2014;Zare et al, 2020). It should be pointed out that Cu would…”

mentioning

confidence: 99%

A numerical study on thermal deformation of through silicon via with electroplating defect

Hou,

Qiu,

Zhao

et al. 2024

MMMS

View full text Add to dashboard Cite

show abstract

“…Since TSV is used in various forms depending on the requirement of the chip, it is necessary to study the shape, stacking method, and arrangement structure, which are the variables that can affect the electrical characteristics of TSV [64,65]. Jeong et al [66] have compared the impedance values for different TSV shapes such as cylindrical, square, elliptical, and triangular shapes.…”

Section: Electrical Properties Of Tsvmentioning

confidence: 99%

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

Self Cite

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With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

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“…Silicon-based materials are extensively used in microelectromechanical systems, solar panels, and other electronic and semiconductor industries [1][2][3]. Silicon through-holes applied in chip packaging have extremely large hole depths and large aspect ratios [4]. The depths and widths of the microholes affect the groove's filling effect [5], which in turn affects the quality and performance of three-dimensional chip integration.…”

Section: Introductionmentioning

confidence: 99%

Use of the Airy beam to extend the micro-hole measurement range of an OCT system

Fan

Xia

Dong

et al. 2023

Meas. Sci. Technol.

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Optical Coherence Tomography (OCT) has the advantage of high precision in measuring micrometre-scale precision structures, but its measurement range is limited by the correlation with Rayleigh length of Gaussian beam.Therefore, this study used the Airy beam to extend the focal depth of the OCT system. The system’s coupled power was increased by 7.34 times when the sample position was at an optical defocus of 3 mm. Measurements of the resolution plate and silicon wafer sample showed that Airy beam OCT had a lateral resolution of 7.4 μm and the focal depth was >6 mm. While the focal depth of the Gaussian beam OCT with the equivalent lateral resolution was less than 1 mm. This improved OCT system demonstrates significant potential for sample measurements at large aspect ratios in the industrial surface detection field.

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Cu Protrusion of Different through-Silicon via Shapes under Annealing Process

Cited by 19 publications

References 29 publications

A numerical study on thermal deformation of through silicon via with electroplating defect

A numerical study on thermal deformation of through silicon via with electroplating defect

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Use of the Airy beam to extend the micro-hole measurement range of an OCT system

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