Cu surface treatment influence on Si adsorption properties of CuSiN self-aligned barriers for sub-65nm technology node

Chhun, S.; Gosset, L.G.; Michelon, J.; Girault, V.; Vitiello, J.; Hopstaken, M.; Courtas, S.; Debauche, Christian; Bancken, P.; Gaillard, Nicolas; Bryce, George; Juhel, M.; Pinzelli, L.; Guillan, J.; Gras, R.; Schravendijk, B. van; Dupuy, Jérôme; Torrès, J.

doi:10.1016/j.mee.2006.09.013

Cited by 17 publications

(8 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many of the reported methods involve either doping the Cu lines with a few percent of select alloying elements, [376][377][378][379][380][381][382] or selectively forming an additional surface passivation layer material between the DB and Cu. [383][384][385][386][387][388][389][390][391][392][393] In most cases, these methods involve additional processing steps separate from the DB deposition process. However, one method that has been integrated with the DB deposition involves selectively forming a CuSiN interfacial layer between the DB and Cu.…”

Section: N3037mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

View full text Add to dashboard Cite

Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

show abstract

Section: N3037mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

View full text Add to dashboard Cite

show abstract

“…The industry is replacing SiO 2 with a low‐ k dielectric and the Al conductor with Cu (Hoofman et al , 2005), because of many advantages (Wang et al , 2005; Hsia, 2006; Yazdani, 2006). This also brings new challenges to wire bonding (Degryse et al , 2005; Tagami et al , 2005; Viswanath et al , 2005; Zhao, 2005; Chhun et al , 2006; Dang et al , 2006; Gottfried et al , 2006; Huang et al , 2006; Kim et al , 2006; Leduc et al , 2006; Yeh et al , 2006; Fiori et al , 2007c; Inoue et al , 2007; Kregting et al , 2007; van der Sluis et al , 2007a, b; van Driel, 2007; van Gils et al , 2007; van Hal et al , 2007; Srikanth et al , 2008).…”

Section: Challenges In Fine and Ultra‐fine Pitch Wire Bondingmentioning

confidence: 99%

Fine and ultra‐fine pitch wire bonding: challenges and solutions

Zhong

2009

Microelectronics International

View full text Add to dashboard Cite

PurposeThe purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.Design/methodology/approachDozens of journal and conference articles published recently are reviewed.FindingsThe problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.Research limitations/implicationsBecause of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.Originality/valueThis paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.

show abstract

“…Low-k materials introduce new challenges to the mechanical integrity of IC devices (Zhao, 2005) and wire bonding. Cu electromigration is also a key issue that limits the lifetime of advanced interconnection systems (Chhun et al, 2006). A critical challenge for the integration of porous low-k materials is their degradation during different processes (Baklanov et al, 2006).…”

Section: Wire Bonding and New Challengesmentioning

confidence: 99%

Wire bonding using insulated wire and new challenges in wire bonding

Zhong

2008

Microelectronics International

View full text Add to dashboard Cite

Purpose -This paper attempts to review recent advances in wire bonding using insulated wire and new challenges in wire bonding for advanced microelectronics packaging. Design/methodology/approach -Dozens of journal articles, conference articles and patents published or issued in 2004-2007 are reviewed. Findings -The advantages and problems/challenges related to wire bonding using insulated wire are briefly analysed, and several solutions to the problems and recent findings/developments related to wire bonding using insulated wire are discussed. Research limitations/implications -Because of page limitation of the paper, only brief review is conducted. Further reading is needed for more details. Originality/value -This paper attempts to provide introduction to recent developments and the trends in wire bonding using insulated wire. With the references provided, readers may explore more deeply by reading the original articles and patent documents.

show abstract

Cu surface treatment influence on Si adsorption properties of CuSiN self-aligned barriers for sub-65nm technology node

Cited by 17 publications

References 9 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Fine and ultra‐fine pitch wire bonding: challenges and solutions

Wire bonding using insulated wire and new challenges in wire bonding

Contact Info

Product

Resources

About