CUDA memory optimisation strategies for motion estimation

Abstract

As video processing technologies continue to rise quicker than central processing unit (CPU) performance in complexity and image resolution, data-parallel computing methods will be even more important. In fact, the high-performance, data-parallel architecture of modern graphics processing unit (GPUs) can minimise execution times by orders of magnitude or more. However, creating an optimal GPU implementation not only needs converting sequential implementation of algorithms into parallel ones but, more importantly, needs cautious balancing of the GPU resources. It requires also an understanding of the bottlenecks and defect caused by memory latency and code computing. The defiance is even greater when an implementation exceeds the GPU resources. In this study, the authors discuss the parallelisation and memory optimisation strategies of a computer vision application for motion estimation using the NVIDIA compute unified device architecture (CUDA). It addresses optimisation techniques for algorithms that surpass the GPU resources in either computation or memory resources for CUDA architecture. The proposed implementation reveals a substantial improvement in both speed up (SU) and peak signalto-noise ratio (PSNR). Indeed, the implementation is up to 50 times faster than the CPU counterpart. It also provides an increase in PSNR of the coded test sequence up to 8 dB. 2 Architecture and memory spaces of graphics processing units In the NVIDIA GPU-based architecture, parallelisation is obtained through the execution of tasks in a number of stream processors

Fraction Execution Resolver Using a Hybrid Multi-CPU/GPU Encoding Scheme

“…Finally, the kernel (GPU) returns to the caller (CPU) a set of indexed arrays-concerning the whole search area [40]-with the minimum distortion ratios as well as the corresponding motion vector. To minimize the data transfer costs, memory optimization strategies are used between the kernel and the host [41,42].…”

On Combining Wavefront and Tile Parallelism with a Novel GPU-Friendly Fast Search

“…The minimum distortion ratios from the previous processing step, which concerns the whole search area, are the motion vectors selected for the next step in the Host program (CPU). Memory optimization strategies are used to confine the data transfers between the host and the kernel [36]. The minimum estimated RD-ratio is defined from Equation (1), which is also computed inside the kernel (GPU program created with a modified C programming language).…”

“…For that reason, to minimize the transfer data costs, the kernel (GPU program) is implemented as a single program that executes both the A and B functions described above, at once, without having to return partial results to the host. When the 4-phase search cycle is completed, then and only then, the host receives back the final minimum RD cost array with respective MVs [36]. From this point so far, the CPU thread continues with the next step.…”

A Novel Parallel Motion Estimation Design and Implementation on GPU

“…For better combining the previous parallelization techniques on CPU, [9] proposed two joint algorithms which are based on WPP and on a traditional GOP-based division pattern. On the other hand, the effective parallel implementation of crucial parts in ME is very important [10], [11]. Sayadi et al [10] propose the memory optimization strategies for better making full use of GPU resources and accelerating ME.…”

“…On the other hand, the effective parallel implementation of crucial parts in ME is very important [10], [11]. Sayadi et al [10] propose the memory optimization strategies for better making full use of GPU resources and accelerating ME. Because the calculation of SAD or SSD is a time-consuming part in ME, [11] proposes a fast parallel implementation of SAD or SSD using parallel reduction technique.…”