Current and Emerging Trends in the Design of Digital-to-Analog Converters

Abstract

The advent of digital computing, coupled with the continued scaling of CMOS devices, has led to the rapid growth in theory and applications of digital signal processing (DSP). In order to leverage the available increase in speed, complexity, and integration, high-performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are needed to ensure the highest signal fidelity when moving between the analog and digital domains. Traditionally, high-speed ADCs have attracted more attention in the research and scientific community than their DAC counterparts, mainly due to the inherent shift towards receivers in the study and analysis of radio systems [1].This chapter aims to describe some of the design challenges and emerging trends for high-speed and high-resolution digital-to-analog converters. Section 3.1 presents an overview of the digital-to-analog conversion process. Section 3.2 delves into DAC characterization by outlining different sources of error and metrics used to quantify the DAC performance. A summary of DAC topologies and circuit limitations in the context of current-steering (CS) DACs is provided in Sects. 3.3 and 3.4, respectively. Section 3.5 details four major considerations in the design space of CS DACs. Realizing that the segmented architecture is the de facto standard in high-resolution DACs, a supplemental approach to segmentation is presented in Sect. 3.6. An in-depth survey of current and emerging architectural trends in high-performance DACs is discussed in Sect. 3.7. Finally, Sect. 3.8 concludes with a summary and a brief discussion on future directions.

Accuracy and speed limitations in DACs across CMOS process technologies

“…As a result, technology scaling has little or no effect on the overall mismatch error. Nevertheless, a large V OD is critical in improving the matching in current-mode circuits [2,3,7]. Yet, the limitations in headroom impose restrictions on the maximum possible V OD .…”

“…Since, the cell impedances are a function of the excited code, Z DAC (s) changes as the input code changes, thus leading to code-dependent distortion [3]. The degree of distortion depends on Z CELL (s), which is derived subsequently.…”

“…3(c). In this case, DAC-A 3 The DAC core is comprised of nfet transistors for M1, M2, M3-M4 and high voltage nfets for M5-M6. The input signal to the DAC is retimed with an ideal Verilog-A latch and inverter buffer chain 4 The LSB current mismatch has σ(ΔILSB)/ILSB =1.3%.…”

“…This is made possible with the continued scaling of CMOS process technologies that offer the benefits of high levels of integration along with low power consumption, fast switching speed, and reduced die area. However, with the emergence of sub-100 nm process nodes, data converter designers are facing numerous challenges in achieving target specifications while maintaining high yield [2,3,4].…”

Principles of Signal Conversion: A Brief Tutorial

“…If the plant is analog, then the signal must be transformed to analog signal. The digital control signal goes through two conditioning process before it is transformed to analog control signal: coding for determining amplitude of the analog signal for each predetermined interval and holding for generating discrete signal [11]. Figure 2 describes an example of D/A signal conversion.…”