Fig. 4. Simulation result using LPE netlist.produced. HSPICE is then used to resimulate the delay of this LPE extracted netlist. The simulation result is shown in Fig. 4. The maximum rise delay is 12.5 ns while the maximum fall delay is 14.1 ns. It gives a reasonable explanation that parasitic effects are to be blamed for the degradation of the speed performance.
VII. CONCLUSIONSeveral dynamic CMOS comparators are proposed with a number of advantages. The transistor count is much less than that of the other similar designs, and the total area size is less than that of the prior comparators. Furthermore, the noise immunity is better than the prior comparators. Although it has high fan in, the number of series transistors in the N-transistor evaluation block is two, which in turns reduce the pull down delay.
REFERENCES[1] C.Abstract-This brief presents a quantitative analysis of the operating characteristics of three-phase diode bridge rectifiers with ac-side reactance and constant-voltage loads. We focus on the case where the ac-side currents vary continuously (continuous ac-side conduction mode). This operating mode is of particular importance in alternators and generators, for example. Simple approximate expressions are derived for the line and output current characteristics as well as the input power factor. Expressions describing the necessary operating conditions for continuous ac-side conduction are also developed. The derived analytical expressions are applied to practical examples and both simulations and experimental results are utilized to validate the analytical results. It is shown that the derived expressions are far more accurate than calculations based on traditional constant-current models.