2012 International Conference on Signals and Electronic Systems (ICSES) 2012
DOI: 10.1109/icses.2012.6382228
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Current controlled delay line elements' improvement study

Abstract: The chain of delay elements creating delay lines are the basic building blocks of delay locked loops (DLLs) applied in clock distribution network in many VLSI circuits and systems. In the paper Current Controlled delay line (CCDL) elements with Duty Cycle Correction (DCC) has been described and investigated. The architecture of these elements is based on Switched-Current Mirror Inverter (SCMI) and CMOS standard or Schmitt type inverters. The primary characteristics of the described CCDL element have been compa… Show more

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Cited by 5 publications
(1 citation statement)
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“…The circuit in Figure 2 requires synchronized clock sources responsible for the triggering of Q 1 and Q 2 . There are common approaches that incorporate either an adjustable delay obtained with the use of either the Direct Digital Synthesis (DDS) circuit ( Figure 3a) [10][11][12] or an analogue approach based on the ramp source and a programmable comparator (see Figure 3b) [10][11][12]. The analogue solution is relatively inexpensive; however, several drawbacks of an analogue delay line may decrease the functionality of the laser driver.…”
Section: Circuit Timingmentioning
confidence: 99%
“…The circuit in Figure 2 requires synchronized clock sources responsible for the triggering of Q 1 and Q 2 . There are common approaches that incorporate either an adjustable delay obtained with the use of either the Direct Digital Synthesis (DDS) circuit ( Figure 3a) [10][11][12] or an analogue approach based on the ramp source and a programmable comparator (see Figure 3b) [10][11][12]. The analogue solution is relatively inexpensive; however, several drawbacks of an analogue delay line may decrease the functionality of the laser driver.…”
Section: Circuit Timingmentioning
confidence: 99%