Current mirror test structures for studying adjacent layout effects on systematic transistor mismatch

A Review of Test Structures for Characterising Microelectronic and MEMS Technology

“…Recent examples of innovative matching test structures include examinations of the effects of asymmetrical metal layout on a high-precision current mirror circuit [55,56] and the discovery of a systematic mismatch effect caused by spin processing during photolithography [57].…”

Electrical characterization and modeling of advanced nano-scale ultra thin body and buried oxide MOSFETs and application in circuit simulations

“…Additionally, local variability, usually referred to as mismatch, can be further divided into systematic and stochastic. Systematic mismatch stems from sources that can be predicted, like asymmetries in layout [37] and therefore it can be reduced to a certain degree by following more mismatch-aware practices, like for example use of "dummies" in MOS transistors conception [38].…”

Triple-gate junctionless MOSFETs

“…This kind of variation is due to the processing steps and is independent of the distance between the devices under study. Its impact on the performance of a device is clearly reflected as it determines the maximal obtainable accuracy within a certain technology [10]. Systematic variations arise from predictable sources, such as asymmetries in a layout [11] and can be controlled through mismatch-aware guidelines like the use of dummies [12].…”

“…These aforementioned mechanisms degrade the device's performance by affecting: 1) the threshold voltage, 2) the gate depletion, 3) the quantum mechanical effects, 4) the carrier screening and 5) the mobility of the carriers. It has been proven that these phenomena are of crucial importance and cannot be neglected [10].…”