Current percolation in ultrathin channel nanocrystalline silicon transistors

Abstract

The ultrathin channel nanocrystalline silicon transistor shows greatly improved switching performance and has demonstrated its candidacy for low power applications. In this work, by careful observation of the current-voltage and threshold voltage characteristics, we find that current percolation occurs when the channel is thinner than 3.0 nm due to strong quantum confinement induced large potential variations over the channel. We show that the device channel width must be at least 0.3 m to avoid percolative "pinch off" for 0.5 m channel length devices. Theoretical analysis performed on the devices agrees well with the experimental data and provides important guidelines to model and optimize the devices for circuit design. © 2008 American Institute of Physics. ͓DOI: 10.1063/1.2965807͔There has been significant interest in silicon nanostructures for electronics, photovoltaic, and optoelectronic applications, including zero-dimensional silicon nanocrystallites, one-dimensional ͑1D͒ quantum wires, and two-dimensional ͑2D͒ thin layers. 1-3 All these structures are designed to use the quantum confinement effect to enhance the device's performance. To design transistors for integrated electronics, however, the ideal structure must also be compatible with conventional silicon device processing. The 2D silicon layers appear to be the best choice for current fabrication techniques due to the planar geometry that is utilized in current complementary metal oxide semiconductor technology. Recently, by controlling the deposition ͑chemical vapor deposition͒ process at a very low deposition rate, ultrathin ͑Ͻ5 nm͒ flat nanocrystalline silicon ͑nc-Si͒ layers were achieved and applied as the channel for transistors in low power applications. 4 It is proven that using such an ultrathin channel effectively improves the switching performance of thinfilm transistors in nc-Si. 5 When the channel becomes thinner, the OFF-state leakage current I OFF decreases significantly, which is attributed to the stronger quantum confinement effect along the channel thickness direction. The subthreshold swing ͑S͒ also becomes steeper because the effect of gate voltage on the channel surface potential increases. Low I OFF and steep S result in a high I ON / I OFF ratio. 5 The high I ON / I OFF ratio will enable the transistors to be used to design integrated electronics on arbitrary substrates for the applications, where low power and fast access times are demanded.However, when the nc-Si layer becomes very thin, even the smallest thickness variation can result in highly random potential fluctuations due to the strong quantum confinement effect along the channel thickness direction, 6 and charge traps at grain boundaries ͑GBs͒ will also deplete the nc-Si grains of free carriers. 7 These will make the carrier transport from the source to the drain through the device channel become much more complicated, and result in electrical characteristics that may not be described by conventional fieldeffect transistor ͑FET͒ models. In the present study, current ...

Significant improvement of spray pyrolyzed ZnO thin film by precursor optimization for high mobility thin film transistors

“…In nanocrystalline ZnO, the electron trapping sites at grain boundaries control electron conduction [20][21][22][23][24] . Fig.…”

Quantum Information and Nuclear Magnetic Resonance Parameters

“…Em uma ordem de magnitude menor, efeitos quânticos começam a se manifestar possibilitando aos elétrons pular de um condutor para outro, perdendo-se assim as características básicas do dispositivo. 27 O trabalho que deu início as pesquisas sobre os problemas relacionados aos processos de miniaturização, em particular por problemas dentro da teoria da computação e dos sistemas computacionais, foi o estudo entre consumo de energia e computação, feito por R. Landauer, no ano de 1961. 28 Em 1973, C. Bennett mostrou matematicamente a possibilidade de realizar operações computacionais reversíveis, resultando na possibilidade de desenvolvê-las sem dissipação de energia.…”

Critical distance method for predicting the tail part of the threshold voltage distribution

“…Because of shrinking of device size down to 10 nm, the statistical variations due to the traps and dopants becomes more severe. Moreover, it is also problematic that there are an abnormally large threshold voltage (VT) shift that may belong to the 6-sigma tail of the statistical distribution [2]- [5]. It has been reported that chained traps and dopants forming a cluster of potential peaks on the channel surface results in the tail distribution.…”