Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

Majumder, Alak; Bhattacharjee, Pritam

doi:10.1109/inis.2017.53

Cited by 6 publications

(1 citation statement)

References 9 publications

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“…But because they are connected to the same system clock, the current pumping (i.e., i(t) and di/dt) happens across these components in spite of they are not participating to the on-chip activity at that point of time. In [29], we have already projected how the implementation of clock gating has helped in the minimization i(t) and di/dt as well as the curbing of PSN. Nevertheless, we have notion that if VFC and the clock gating are used together in an on-chip single platform, then there can be possible reduction of PSN.…”

Section: Probable Solution To Reduce the On-chip Power Supply Noisementioning

confidence: 99%

Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

Bhattacharjee¹,

Rana²,

Majumder³

2020

Recent Trends in Communication Networks

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The on-chip activities of any modern IC are always inhibited due to the occurrence of power supply noise (PSN) in the chip power line. From many decades, researchers are pondering on what are the major issue of this PSN occurrence and how it can be suppressed without interfering the actual chip functioning. In the course of time, it is found that the uncontrolled triggering of the on-chip system clock and the unguarded on-chip power line is instigating the two major factors for the occurrence of PSN i.e., i(t) → instantaneous current and di/dt → current ramp or the rate of change of current over time. Both i(t) and di/dt are also the sub-factors to rise the PSN components like resistive noise and inductive noise respectively. In this chapter, we light upon the occurrence of resistive and inductive noise as well as depict their individual impact on the PSN occurrences. There is also discussion on how PSN is suppressed over the years in spite of facing challenges in the execution of suppression techniques. This chapter even concludes on the suitable ways for mitigating PSN in the contemporary era of delivering complex on-chip features.

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Section: Probable Solution To Reduce the On-chip Power Supply Noisementioning

confidence: 99%

Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

Bhattacharjee¹,

Rana²,

Majumder³

2020

Recent Trends in Communication Networks

Self Cite

View full text Add to dashboard Cite

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On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies

Bhattacharjee

Trivedi

Majumder

2022

International Journal of Electronics

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Transient Suppression Scheme for Mitigation of High-Performance VRM Intricate Load Profiles

Halivni

Urkin

Peretz

2022

2022 IEEE Applied Power Electronics Conference and Exposition (APEC)

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Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

Cited by 6 publications

References 9 publications

Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies

Transient Suppression Scheme for Mitigation of High-Performance VRM Intricate Load Profiles

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