Current source based standard-cell model for accurate timing analysis of combinational logic cells

Mahmoud, M. A.; Wassal, Amr G.; El-Rouby, Alaa E.; Guindi, Rafik

doi:10.1109/icecs.2013.6815409

Cited by 3 publications

(5 citation statements)

References 7 publications

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“…In the past decade, CSM has been developed as various forms [2] - [8]. The CSM for a combinational logic gate in [7] consists of a nonlinear voltage-controlled current source I o (V i , V o ) at the output node, three nonlinear voltage-dependent capacitive components including input and output parasitic capacitances…”

Section: Previous Current Source Modelsmentioning

confidence: 99%

“…In [8], it was pointed out that the model of combinational logic cells in [7] cannot handle the cases when the gate output is connected to a small load capacitance while applying fast ramp signals with small transition times at the gate input. So the authors in [8] extended and enhanced the CSM in [7] by adding a calibration capacitance (C calb ) at the output node.…”

Section: Previous Current Source Modelsmentioning

confidence: 99%

“…So the authors in [8] extended and enhanced the CSM in [7] by adding a calibration capacitance (C calb ) at the output node. The calibration capacitance is parallel to the characterized output capacitance.…”

Section: Previous Current Source Modelsmentioning

confidence: 99%

“…The calibration capacitance is parallel to the characterized output capacitance. In [8], the C calb value is given in this way: for single input logic gates (such as the inverter), C calb is equal to the input capacitance of the gate; for two-input gates, C calb is equal to twice of the input capacitance of the gate, and so on. CSM in [8] will be referred as Model No.…”

Section: Previous Current Source Modelsmentioning

confidence: 99%

“…Model No.1 was used in [9] to test a four-inverter chain, and the result showed obvious propagated error. In [8], they tried to modify the model by adding a calibration capacitance C calb parallel to the characterized output capacitance. However, it still has two problems.…”

Section: Multiple-input Switching Effectmentioning

confidence: 99%

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Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysis

Chen

Kim

2015

VLSI Design, Automation and Test(VLSI-Dat)

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Many current source models (CSMs) have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade. However, most of them may suffer from large delay errors for multiple-stages of combinational logic gates. This paper presents an extended CSM which can provide high accuracy in both single-stage and multiple-stage combinational logic gates. The proposed CSM consists of voltage-controlled current source, input and output parasitic capacitances, Miller capacitance and calibration input capacitance parallel to the characterized input capacitance. The calibration input capacitance helps to model the input node more accurately. In experiments, the proposed CSM outperformed the benchmark CSMs in the average root-mean squared error (RMSE) and the average 50%-to-50% gate delay error.

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Section: Previous Current Source Modelsmentioning

confidence: 99%