Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power

Nayak, Debasish; Acharya, Debiprasad Priyabrata; Mahapatra, Kamalakanta

doi:10.1007/s00034-016-0466-5

Cited by 19 publications

(6 citation statements)

References 21 publications

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“…SNM improvement techniques mainly include transistor width modulation, word-line voltage modulation and bit-line voltage modulation. Some techniques [10][11][12][13][14] when applied to the memory cell may lead to contradictory effects; for example, improvement in stability is obtained at the cost of area or leakage power, so optimization of various parameters as per the requirement is a challenge.…”

Section: Related Workmentioning

confidence: 99%

“…Perimeter of drain = P D1 = Perimeter of source = P S1 = W + 2W D (5) In the same way, the estimation of area and perimeter of drain and source can be done for two finger transistors: Similarly, the estimation of area and perimeter of drain and source for three finger transistors is given in Equations ( 10)- (13).…”

Section: Fingering In Mos Transistormentioning

confidence: 99%

“…Perimeter of source = Ps 3 = 2 × 2Ws + (1/3)W = 4Ws +W/3 = 4W D +W/3 = P D3 (13) When the number of fingers (N f ) is even = 2k (where k is an integer), the number of drain diffusion is k and the number of source diffusion is (k + 1) while the finger width reduces to W/2k, so the total area for drain diffusion is reduced by half and the perimeter is also less than the perimeter of a one finger transistor.…”

Section: Area Of Drainmentioning

confidence: 99%

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A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

Tripathi¹,

Chauhan

Singh³

2018

JLPEA

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The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology.

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Section: Related Workmentioning

confidence: 99%

Section: Fingering In Mos Transistormentioning

confidence: 99%

Section: Area Of Drainmentioning

confidence: 99%

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A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

Tripathi¹,

Chauhan

Singh³

2018

JLPEA

View full text Add to dashboard Cite

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“…The outputs S and Cout are computed using the following expressions. S= "A⊕B⊕C" ………….. (1) Cout=A.B + B.C +C.A…....... 2The 1-bit CMOS full adder cell is shown in Fig1. The 1-bit full adder cell consists of 14 transistors.…”

Section: Introductionmentioning

confidence: 99%

“…The 1-bit full adder cell consists of 14 transistors. Designing of logic gates with such large no of transistors makes the design area inefficient, increases power consumption, reduction in speed [1]. Dynamic power dissipation and larger delay is caused due to large PMOS transistors in pull up network that results in high input capacitances.…”

Section: Introductionmentioning

confidence: 99%