Current Status of Research and Development for Three-Dimensional Chip Stack Technology

Abstract

The national project of “Ultra High-Density Electronic System Integration” was initiated in 1999. This is the first project to focus on a niche area between electronic devices and systems. It aims to develop technologies for overcoming the problems in terms of performance of electronic systems. Three-dimensional (3D) LSI chip stacking, optoelectronics hybrid integration, and optimum circuit design are the technology categories. For the 3D stacking technology, a chip-based stacking technology is under extensive development that includes wafer preparation for chip stacking, wafer thinning, chip stacking, and inspection and testing. In this paper, the current development status of the 3D stacking technology, called V-STACK technology, is introduced.

Crank‐shaped and Y‐shaped through‐hole interconnections filled with Au‐Sn solder

“…Through-hole interconnections that form precise through holes in silicon (Si) and other substrates and create three-dimensional electrical wiring filled with a conductor are a key technology for achieving next-generation electronic device packages, and research and development are under way around the world [1][2][3][4][5]. We have been working on the development of wafer-level packages (WLP) using through-hole interconnections for use in MEMS devices and high-frequency devices, as well as in image sensors [6].…”

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

“…[1][2][3] Significant decreases in power consumption, size and weight can be expected by the application of 3D packaging. 2) In particular, 3D packaging with through-silicon-via (TSV) can minimize the total length of the current path as well as signal delay.…”

“…4,5,9) Cu is frequently used as a seed layer due to its low cost and lower electrical resistivity. 1,[10][11][12] However, Au can be used instead of Cu due to its chemical stability in electrolytes and good oxidation resistance, which removes the need for oxide pre-cleaning on the seed layer.…”

“…For Cu deposition, an electro-plating method 1,13) is preferred to an electroless process 14) because the latter has a low plating speed 15) and an inability to form a deposit layer more than 1 mm thick. 16) However, when an electroplating method is applied, defects such as voids or fillets can be produced during Cu plugging.…”

“…16) However, when an electroplating method is applied, defects such as voids or fillets can be produced during Cu plugging. 1,14,17) To overcome these issues, chemical additives may be added 18) and/or the current waveform 19) can be modified. In this study, modification of the current waveform was used to avoid defects in the Cu plugs.…”