Custom Memory Management Methodology

Catthoor, Francky; Wuytack, Sven; Greef, Eddy De; Balasa, Florin; Nachtergaele, Lode; Vandecappelle, Arnout

doi:10.1007/978-1-4757-2849-1

Cited by 348 publications

(102 citation statements)

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“…In addition, several authors have addressed the problem of laying out scalar variables to make effective use of address generation units in embedded processors [10]. The IMEC group has used several transformations and advocated the use of special hardware for reducing the effect of address arithmetic overhead [4,6,13,14]. Gupta etl al.…”

Section: Related Workmentioning

confidence: 99%

Address code and arithmetic optimizations for embedded systems

Ramanujam¹,

Krishnamurthy²,

Hong³

et al.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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An important class of problems used widely in both the embedded systems and scientific domains perform memory intensive computations on large data sets. These data sets get to be typically stored in main memory, which means that the compiler needs to generate the address of a memory location in order to store these data elements and generate the same address again when they are subsequently retrieved. This memory address computation is quite expensive, and if it is not performed efficiently, the performance degrades significantly. In this paper, we have developed a new compiler approach for optimizing the memory performance of subscripted or array variables and their address generation in stencil problems that are common in embedded image processing and other applications. Our approach makes use of the observation that in all these stencils, most of the elements accessed are stored close to one other in memory. We try to optimize the stencil codes with a view of reducing both the arithmetic and the address computation overhead. The regularity of the access pattern and the reuse of data elements between successive iterations of the loop body means that there is a common sub-expression between any two successive iterations; these common sub-expressions are difficult to detect using state-ofthe-art compiler technology. If we were to store the value of the common sub-expression in a scalar, then for the next iteration, the value in this scalar could be used instead of performing the computation all over again. This greatly reduces the arithmetic overhead. Since we store only one scalar in a register, there is almost no register pressure. Also all array accesses are now replaced by pointer dereferences, where the pointers are incremented after each iteration. This reduces the address computation overhead. Our solution is the only one so far to exploit both scalar conversion and common sub-expressions. Extensive experimental results on several codes show that our approach performs better than the other approaches.

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Section: Related Workmentioning

confidence: 99%

Address code and arithmetic optimizations for embedded systems

Ramanujam¹,

Krishnamurthy²,

Hong³

et al.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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show abstract

“…In a typical ASDSP the power consumed by memory accesses is a substantial part of the total consumption. By memory management the number of accesses to large memories is reduced by rescheduling the arithmetic operations and utilizing memory hierarchies [5].…”

Section: B Memory Managementmentioning

confidence: 99%

“…For this scheduling to be as effective as possible, careful investigation of the memory access pattern for various algorithmic transformations is done [5].…”

Section: Hardware Mappingmentioning

confidence: 99%

Implementation issues for acoustic echo cancellers

Berkeman

Öwall²,

Torkelson³

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356)

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Abstract-The high computational complexity of acoustic echo cancellation algorithms requires application specific implementations to sustain real time signal processing with affordable power consumption. This is especially true for systems where a delayless approach is considered important, e.g. wireless communication systems. The proposed paper presents architectural considerations to reach a feasible hardware solution.

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“…Memory access pattern analysis has been also used for source code transformation or data layout optimization [10] [6]. Catthoor et al observed that the source code should be first optimized to generate the optimal memory access patterns for a given memory architecture.…”

Section: Related Workmentioning

confidence: 99%

“…They proposed several optimization techniques. For example, they pack the data structures according to their size and bit-width and allocate them into memory modules to minimize the memory cost [10]. They examine the memory access patterns in the source code to estimate the memory system performance and apply transformation techniques.…”

Section: Related Workmentioning

confidence: 99%

Memory access pattern analysis and stream cache design for multimedia applications

Lee¹,

Park²,

Ha³

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

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Memory system is a major performance and power bottleneck in embedded systems especially for multimedia applications. Most multimedia applications access stream type of data structures with regular access patterns. It is observed that conventional caches behave poorly for stream-type data structure. Therefore, prediction-based prefetching techniques have been extensively researched to exploit the regular access patterns. Prefetching, however, may pollute the cache if the prediction is not accurate and needs extra hardware prediction logic. To overcome these problems, we propose a novel hardware prefetching technique that is assisted by static analysis of data access pattern with stream caches. With the proposed stream cache architecture, we could achieve significant performance improvement compared with the conventional cache architecture.

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Custom Memory Management Methodology

Cited by 348 publications

References 0 publications

Address code and arithmetic optimizations for embedded systems

Address code and arithmetic optimizations for embedded systems

Implementation issues for acoustic echo cancellers

Memory access pattern analysis and stream cache design for multimedia applications

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