Custom wide counterflow pipelines for high-performance embedded applications

Childers, Bruce R.; Davidson, Jack W.

doi:10.1109/tc.2004.1261825

Cited by 3 publications

(2 citation statements)

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“…In instruction caches, due to the high spatial and temporal locality exhibited by loops in the instruction stream, these auxiliary structures are accessed more often. This is particularly advantageous for embedded applications as most of the execution time in embedded applications is spent in tiny loops known as computational kernels [21,72].…”

Section: Architecture Level Techniques For Power Reductionmentioning

confidence: 99%

“…It has been shown that in embedded applications, these critical code segments, which account for 1% of the total instructions, execute on an average for 50 % of the time [72]. In applications such as GSM speech coding, ADPCM coding, image compression and decompression, MPEG and G.721 voice coding one simple kernel loop typically accounts for a substantial amount of the execution time [21]. Table 3.1 lists the frequent tiny loop statistics for the MediaBanch [43] benchmark suite, which also confirms the published results.…”

Section: Instruction Cache Hierarchy and Embedded Systemsmentioning

confidence: 99%

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Customizable instruction cache hierarchy for embedded systems

Kugan¹

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First of all, I would like to take this opportunity to express my sincere gratitude to my supervisor Dr. Thambipillai Srikanthan, for his guidance, help and patience. He has provided me with numerous valuable ideas, insights, and comments throughout the course of this research. He has also been very understanding and supportive. I am very fortunate to have him as my thesis advisor. I also would like to take this opportunity to thank Dr. Christopher T. Clarke for suggesting several corrections and improvements during many discussions I had with him. And, thanks to Mr. Saurav Bhattacharyya for his helpful suggestions and continuous encouragements. I benefited a lot from them. Special thanks to Mr. Jagadeesh R. George and Mr. Ashish Panda for agreeing to proof read this thesis, in spite of their busy schedule. Their comments and suggestions made a big difference to this thesis. I would also like to take this opportunity to thank all the administrative and supportstaff at the CHiPES. I am especially grateful to Ms. Nah Kiat Joo, Ms. Merilyn Yap and Mr. Chua Chiew Song for all the help, when it mattered most. As always, I am grateful to my family and friends for their tremendous support and encouragement. Especially, I thank my mother and father for all the advice that they have offered me over these years and for motivating me to pursue higher-studies. Many other people contributed to the success of this work and while I would like to acknowledge individually each by name, I would inevitably leave out deserving friends and relatives. I apologize for such omission and convey my respect and admiration to all who contributed to the extraordinary experiences I have been fortunate to enjoy.

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Section: Architecture Level Techniques For Power Reductionmentioning

confidence: 99%

Section: Instruction Cache Hierarchy and Embedded Systemsmentioning

confidence: 99%