Customizable Fault Tolerant Caches for Embedded Processors

Abstract

Abstract-The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embedded processors. Concurrently, intra-die and inter-die process variation at future technology nodes will cause defect-free yield to drop sharply unless mitigated. This paper focuses on an architectural technique to configure cache designs to be resilient to memory cell failures brought on by the effects of process variation. Profile-driven re-mapping of memory lines to cache lines is proposed to tolerate failures while minimizing degradation in average memory access time (AMAT) and thereby significantly boosting performance-based die yield beyond that which can be achieved with current techniques. For example, with 50% of the number of cache lines faulty, the performance drop quantified by increase in AMAT using our technique is 12.5% compared to 60% increase in AMAT using existing techniques.

Improving performance and area overhead by reducing the switching table for Self Adaptive cache Memories

“…The hard errors can appear due to process variation, aging, and others [4] [5] [6]. As described in [1] an effective graceful degradation method for set associative cache memories called SAM (Self Adaptive cache Memories) was proposed.…”

Improving cache efficiency via resizing + remapping

“…We view resource scaling as a natural extension to the prior techniques for intelligently turning off portions of the cache for short periods of time, and which requires solving a basic problem of mapping all of memory into the scaled down cache or a scaled up cache i.e., computing a new placement function. We combine the abstraction of conflict sets [13] with run-time reference counts to realize simple (hardware) techniques to dynamically resize the cache to a subset of active components and recompute the placement function. We target the L2 cache because of its larger size and consequently greater impact on energy consumption.…”