Customized MMRF: Efficient Matrix Operations on SIMD Processors

Abstract

Wireless communication and multimedia applications feature a large amount of matrix operations with different matrix size. These operations require accessing matrix in column order. This paper implements a Multi-Grained Matrix Register File (MMRF) that supports multi-grained parallel row-wise and column-wise access. We implement a 4*4 MIMO decoding with the help of MMRF to illustrate the efficient matrix operations on SIMD processors. Experimental results show that, compared with TMS320C64x+, our SIMD processor can achieve about 5.65x to 7.71x performance improvement by employing the MMRF. By customized design technology, we reduce the area and critical-path delay of MMRF by 17.9% and 39.1% respectively.

Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors

“…We target applications that offer embarrassing parallelism, namely the same code is executed by a number of independent threads on different data sets. Such applications can be found in real-world computing problems such as encryption [2], scientific calculations [3], multimedia processing [4] and image processing on large data [5]. Those large computing problems demand designs of multiprocessor systems that can be built on small building block processors like the one we discuss in this paper.…”