Customized on-chip memories for embedded chip multiprocessors

Abstract

Ensuring that most of data accesses are satisfied from on-chip memories is a critical problem for chip multiprocessors, as the cost of an off-chip access can be very high. Particularly, multiple cores that need to access the off-chip memory system may contend with each other for the same buses/pins to get there. While it is possible to structure on-chip memory space as shared memory or private memory, each of these has its own drawbacks. In an attempt to achieve lower power consumption than these conventional memory architectures, this paper proposes and evaluates an application-specific hybrid memory architecture that has both shared and private components. The approach is built upon the idea of capturing the amount of privatelyaccessed and shared data across processors through a polyhedral tool, and using this information to guide memory space partitioning across two dimensions, namely, across parallel processors and across shared and private memory components. We evaluate the resulting memory configurations using a set of benchmarks and compare them to pure private and pure shared architectures. When running the same set of applications with the same code optimizations, our results indicate that the proposed hybrid memory design methodology leads to much less power consumption than the conventional architectures.

Dynamic Shared SPM Reuse for Real-Time Multicore Embedded Systems

“…On-chip memory (cache or SPM) organization and partitioning for data-intensive applications is studied in Kandemir et al [2004] and Ozturk et al [2005Ozturk et al [ , 2006a. Kandemir et al [2004] proposed an approach to dynamically change the organization of shared on-chip memory to adapt to runtime variations in memory requirements and data sharing patterns.…”

“…Kandemir et al [2004] proposed an approach to dynamically change the organization of shared on-chip memory to adapt to runtime variations in memory requirements and data sharing patterns. Ozturk et al [2005] partitioned on-chip memory into several private and shared blocks and assigned these blocks to processor cores by capturing the private and the shared accesses of the cores to data. Moreover, they proposed an integrated data allocation and on-chip memory partitioning based on ILP in Ozturk et al [2006a].…”

Optimizing Data Distribution for Loops on Embedded Multicore with Scratch-Pad Memory

“…It can also access data items on other cores' SPMs by the interconnect bus. Scratch-pad-memory here can be organized as a Virtually Shared SPM (VS-SPM) architecture for on-chip memory that takes advantage of both shared and local SPM [21]. Distinct from the local SPM, SPMs of other cores are referred to as remote SPMs.…”

Compiler-Directed Energy Reduction Using Dynamic Voltage Scaling and Voltage Islands for Embedded Systems

“…Besides voltage island based systems, there are many prior efforts that target at reducing energy consumption of MPSoC-based architectures and chip multiprocessors [15]. For example, Ozturk et al [29] propose an energy-efficient on-chip memory design for embedded chip multiprocessor systems. Manolache et al [25] present a fault and energyaware communication mapping strategy for applications implemented on NoCs.…”