Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

Böhm, Igor; Franke, Björn; Topham, Nigel

doi:10.1109/icsamos.2010.5642102

Cited by 38 publications

(22 citation statements)

References 33 publications

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“…Application speedup over single-core simulation is shown in Chart 2 of Figure 1. The maximum speedup of 4.4× is reached when simulating 16 target cores and even with 64 simulated cores the application shows a speedup of 1.7×.…”

Section: A Motivating Examplementioning

confidence: 99%

“…Currently, ARCSIM supports cycle-accurate simulation of each processor core [2]. However, faithful performance modelling of the overall multi-core system including its memory hierarchy and interconnect is beyond the scope of this paper and subject of our future work.…”

Section: B Contributionsmentioning

confidence: 99%

“…1 shows a comparison of maximum achievable simulation rate in MIPS for a 12-core configuration running a parallel Mandelbrot fractal benchmark on an FPGA, ASIP, and ISS platform. 2 depicts the ratio of interpreted vs. natively executed instructions on the ISS platform.…”

Section: B Fpga Based Multi-core Simulation Approachesmentioning

confidence: 99%

“…For some embedded processors, simulators even exceed the native execution performance of speed-optimised silicon implementations of the target processor [2] whilst, at the same time, providing architectural observability. These remarkable performance levels for single-core instruction set simulation have been enabled by Just-in-Time (JIT) Dynamic Binary Translators (DBT), which rely on advanced compiling techniques for efficient on-the-fly translation of binary code, and powerful simulation hosts providing the necessary CPU performance for efficient native code execution.…”

Section: Introductionmentioning

confidence: 99%

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Scalable multi-core simulation using parallel dynamic binary translation

Almer

Böhm

Koch

et al. 2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (ISS) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (JIT) dynamic binary translation (DBT). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (ISA). We have evaluated our parallel simulation methodology against the industry standard SPLASH-2 and EEMBC MULTIBENCH benchmarks and demonstrate simulation speeds up to 25,307 MIPS on a 32-core x86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead.

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Section: A Motivating Examplementioning

confidence: 99%

Section: B Contributionsmentioning

confidence: 99%

Section: B Fpga Based Multi-core Simulation Approachesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Scalable multi-core simulation using parallel dynamic binary translation

Almer

Böhm

Koch

et al. 2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

Self Cite

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“…To obtain performance results a hardware verified cycle-accurate simulator [6] for the ENCORE extensible processor [1] is used. The ENCORE is largely compatible with the SYNOPSYS ARC 700 processor.…”

Section: Empirical Evaluation 41 Experimental Setupmentioning

confidence: 99%

Compiling for automatically generated instruction set extensions

Murray

Franke

2012

Proceedings of the Tenth International Symposium on Code Generation and Optimization

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The automatic generation of instruction set extensions (ISEs) to provide application-specific acceleration for embedded processors has been a productive area of research in recent years. The use of automatic algorithms, however, results in instructions that are radically different from those found in conventional ISAs. This has resulted in a gap between the hardware's capabilities and the compiler's ability to exploit them. This paper proposes an innovative high-level compiler pass that uses subgraph isomorphism checking to exploit these complex instructions. Our extended code generator also enables the reuse of ISEs designed for one application in another, which may be a newer version of the same application or a different one from the same domain. Operating in a separate pass permits computationally expensive techniques to be applied that are uniquely suited for mapping complex instructions, but unsuitable for conventional instruction selection. We demonstrate that this targeted use of an expensive algorithm effectively controls overall compilation time. The existing, mature, compiler back-end can then handle the remainder of the compilation. Instructions are automatically produced for 179 benchmarks, resulting in a total of 1965 unique instructions. The high-level pass integrated into the open-source GCC compiler is able to use the instructions produced for each benchmark to obtain an average speed-up of 1.26 for the ENCORE extensible processor.

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