DaDianNao: A Machine-Learning Supercomputer

Luo, Tao; Liu, Shaoli; Zhang, Shijin; He, Lei; Wang, Jia; Li, Ling; Chen, Tianshi; Xu, Zhiwei; Sun, Ninghui; Temam, Olivier

doi:10.1109/micro.2014.58

Cited by 1,266 publications

(633 citation statements)

References 30 publications

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“…The use of advanced memory technologies such as embedded DRAM (eDRAM) is explored in [80] to reduce the energy cost in memory access of the weights in DNN. In [81], memristors are used to compute a 16-bit dot product operation with 8 memristors each storing 2-bits.…”

Section: Advanced Technologies For ML Hardware Architecturementioning

confidence: 99%

Hardware Design for Machine Learning

Jawandhiya¹

2018

IJAIA

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Section: Advanced Technologies For ML Hardware Architecturementioning

confidence: 99%

Hardware Design for Machine Learning

Jawandhiya¹

2018

IJAIA

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“…Like most of the standalone accelerators [15][16][17], the accelerator in the proposed system-called reconfigurable application specified processor (RASP), is a loosely coupled configurable engine attached to the AXI bus. Data communication between on-chip memory and external storage, i.e., DDR3 is provided through direct memory access (DMA) in the RASP.…”

Section: System Architecture Overviewmentioning

confidence: 99%

Design and Application Space Exploration of a Domain-Specific Accelerator System

Feng

Wang

et al. 2018

Electronics

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Domain-specific accelerators are a reaction adapting to device scaling and the dark silicon era. This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system. The system is built around accelerator engines and general-purpose processors (GPPs) that make it suitable for intensive computing kernel acceleration and complex control tasks. It is geared toward high-performance radar digital signal processing; we characterize the applications and find that each of them contains a series of serializable kernels. Taking advantage of this discovery, we design an algorithm pool that shares the same computation resource and memory resource, and each algorithm is size reconfigurable. On the other hand, shared on-chip addressable scratchpad memory eliminates unnecessary explicit data copy between accelerators. Performance of the system is evaluated from measurements performed both on an FPGA SoC test chip and on a prototype chip fabricated by CMOS 40 nm technology. The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip. In order to characterize the application of the system, a complex real-life task is adopted, and the results show that it can obtain high throughput and desirable precision.

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“…The rule generated by this can be seen in Figure 4. Figure 5 shows the branch [3][4] [6] converted to rules.…”

Section: Figure 2: Rule-based Architecturementioning

confidence: 99%

“…Chen, et al [3] showed that, when using a custom-designed architecture for running neural networks on parallel processors, they could achieve significant improvements in energy requirements and speed. This method is ideal for a cloud-based service which can be run on multiple servers or across multiple processors more easily.…”

Section: Introductionmentioning

confidence: 99%

Toward Predicting Secure Environments for Wearable Devices

Walter

Riley

et al. 2017

Proceedings of the 50th Hawaii International Conference on System Sciences (2017)

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Wearable devices have become more common for the average consumer. As devices need to operate with low power, many devices use simplified security measures to secure the data during transmission. While Bluetooth, the primary method of communication, includes certain security measures as part of the format, they are insufficient to fully secure the connection and the data transmitted. Users must be made aware of the potential security threats to the information communicated by the wearable, as well as be empowered and engaged to protect it. In this paper, we propose a method of identifying insecure environments through crowdsourced data, allowing wearable consumers to deploy an application on their base system (e.g., a smart phone) that alerts when in the presence of a security threat. We examine two different machine learning methods for classifying the environment and interacting with the users, as well as evaluating the potential uses for both algorithms.

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DaDianNao: A Machine-Learning Supercomputer

Cited by 1,266 publications

References 30 publications

Hardware Design for Machine Learning

Hardware Design for Machine Learning

Design and Application Space Exploration of a Domain-Specific Accelerator System

Toward Predicting Secure Environments for Wearable Devices

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