DAG-aware AIG rewriting: a fresh look at combinational logic synthesis

Abstract

This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inverter Graphs (AIGs), a networks of two-input ANDs and inverters. The optimization works by alternating DAG-aware AIG rewriting, which reduces area by sharing common logic without increasing delay, and algebraic AIG balancing, which minimizes delay without increasing area. The new technology-independent flow is implemented in a public-domain tool ABC. Experiments on large industrial benchmarks show that the proposed methodology scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable or better quality when measured by the quality of the network after mapping.

Hybrid LUT/Multiplexer FPGA Logic Architectures

“…A full table for all architectures showing the architectural minimum area and tolerable CLB increase is shown in Table II. IV. TECHNOLOGY MAPPING USING ABC ABC [13] was used for technology mapping, with modifications that allow for MUX4-embeddable function identification and MUX2-embeddable function indentification in the case of fracturable MUX4s and custom mapping. The internal data structure used within the ABC is an AIG, where the logic circuit is represented using 2-input AND gates with inverters.…”

“…1) Mapping: Using ABC, we performed technologyindependent optimization using the standard resyn2 script included with the ABC distribution [13]. Then, we performed technology mapping with the priority cuts mapper (if command), targeting an LUT size of 6.…”

“…To facilitate the architecture exploration, we developed a CAD flow for mapping into the proposed hybrid CLBs, created using ABC [13] and VPR [14], and describe technology mapping techniques that encourage the selection of logic functions that can be embedded into the MUX4 elements.…”

MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool

“…This need increases the interest for transistorlevel (or "switch-level") CAD tools for digital VLSI design. Traditional approaches and tools work at the gate level and produce optimized Boolean expressions with respect to constraints such as area, delay and power that are then mapped to platforms such as Programmable Logic Devices (i.e., PLAs, PALs, FPGAs) or standard cells (see, e.g., [18], [10], [3], [20], [9], [17], [1], [6], [19], [4], [8], [5], [25], [28], [23], [24]). The design effort is thus greatly reduced but the area and performance are compromised when compared to what can be achieved by a customized transistor-level approach.…”

A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms

“…Even though "more efficient" function representations, like binary decision diagrams (BDDs) [3] or and-invert-graphs (AIGs) [4] were proposed and are widely used in logic synthesis tools, SOP forms still remain an ultimate solution to representing logic functions, mainly due to the fact that most of logic synthesis algorithms are based on processing SOPs. SOPs are usually a starting point for decomposition and technology mapping algorithms [1].…”