DAG based library-free technology mapping

Abstract

This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

“…Reordering only the critical paths produced good delay reduction with minimum area increase. Future works include the addition of reordering and logical effort as a cost function to technology mapping methods devoted to automatic transistor network generation, like [13]. This would make the method more general in application.…”

“…Main contributions of this paper were to point out the importance of transistor reordering when retargeting FPGAs to ASICs, and explain the effect through the concept of logical effort. This concept can be extended to any technology mapping tool that relies on the concept of generating transistor networks [13,24] and is aimed to reduce logical effort [11]. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs.…”

CRDOM : Cell Re-Ordering Based Domino On-The-Fly Mapping

“…Traditionally technology mapping procedures rely on predefined standard cell libraries [9], [10], [11], [12]. Designers even choose to go for cell generator based techniques for mapping complex static gates [13], [14], [15]. Significant attempts are made to decompose a circuit into forest of trees at single fanout points, there by following a tree by tree mapping approach [16], [17].…”

“…This approach tried to perform mapping minimizing logic duplication. A mapping technique focused on minimizing logical effort is presented in [14]. This approach tried to reduce the delay of the overall circuit by reducing the number of series transistors along the critical path.…”

“…This hampers the advantages of forming complex candidate gates. Though delay minimization based on logical effort is presented in [14], [23], they focused on circuits in general and gave little emphasis on Domino logic based circuits. The technology mapping procedure for incompletely specified circuits mentioned in [16] considers nand based DAG covers as the basis.…”