Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. 2004
DOI: 10.1109/vlsit.2004.1345397
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Damage-free CMP towards 32nm-node porous low-k (k = 1.6)/Cu integration

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Cited by 8 publications
(6 citation statements)
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“…This is because that the plasma process makes the PULK film surface become densification and introduce the silanol specie into the PULK film, which increases the dielectric constant value of the PULK film. Recently, some references have reported that the PULK film damages are caused by the dry etching/ashing [14,15], wet cleaning [16], PVD (Physical Vapor Deposition) [17] and CMP (Chemical mechanical polisher) [18,19]. The above mentioned damages not only cause the carbon loss of the PULK film but also make the PULK film performance convert from hydrophobe to hydrophilization.…”
Section: Introductionmentioning
confidence: 99%
“…This is because that the plasma process makes the PULK film surface become densification and introduce the silanol specie into the PULK film, which increases the dielectric constant value of the PULK film. Recently, some references have reported that the PULK film damages are caused by the dry etching/ashing [14,15], wet cleaning [16], PVD (Physical Vapor Deposition) [17] and CMP (Chemical mechanical polisher) [18,19]. The above mentioned damages not only cause the carbon loss of the PULK film but also make the PULK film performance convert from hydrophobe to hydrophilization.…”
Section: Introductionmentioning
confidence: 99%
“…A direct-polish process has applied to the ULK without etch stop layer to reduce an effective dielectric constant in damascene interconnects [6]. However, a porous low-k SiCO:H film often suffers from chemical or mechanical damage during chemical mechanical polishing (CMP) because slurries and cleaning chemicals penetrates into its pores [7,6]. In this study, the directpolish process on organic non-porous fluorocarbon was demonstrated and an optimum direct-polish process condition by nitrogen plasma treatment (NPT) on its surface was investigated.…”
Section: Introductionmentioning
confidence: 99%
“…Filled via stacking is an inevitable element of the buildup printed circuit boards in order to achieve high density interconnections. 1,2 The vias are filled by the copper electrodeposition. Not only the builtup printed circuit boards, but also silicon chips are stacked with the through silicon via (TSV).…”
mentioning
confidence: 99%
“…[3][4][5] For both the filled via and TSV, the vias are filled by the copper electrodeposition. 2 Electrodeposition inhibition at the via outside and acceleration at the via bottom require desired current distributions to fill the vias without voids. The additives of an inhibitor, accelerator, leveler and halogen ion are necessary.…”
mentioning
confidence: 99%