Dark Silicon and the End of Multicore Scaling

Abstract

Since 2005, processor designers have increased core counts to exploit Moore's Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, we use both the ITRS projections and a set of more conservative device scaling parameters. To model singlecore scaling, we combine measurements from over 150 processors to derive Pareto-optimal frontiers for area/performance and power/performance. Finally, to model multicore scaling, we build a detailed performance model of upper-bound performance and lowerbound core power. The multicore designs we study include singlethreaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9× average speedup is possible across commonly used parallel workloads, leaving a nearly 24-fold gap from a target of doubled performance per generation.

Principles of Neuromorphic Photonics

“…The recent shift to multi-core scaling alleviated these constraints, but the breakdown of Dennard scaling has limited the number of cores than can simultaneously be powered on with a fixed power budget and heat extraction rate. Fixed power budgets have necessitated so called dark silicon strategies [20]. Projections for the 8 nm node indicate that over 50% of the chip will be dark [20], meaning unused at a given time.…”

“…Fixed power budgets have necessitated so called dark silicon strategies [20]. Projections for the 8 nm node indicate that over 50% of the chip will be dark [20], meaning unused at a given time. This has led to a widening rift between conventional computing capabilities and contemporary computing needs, particularly for the analysis of complex systems.…”

“…Its occurrence in a variety of different lasing systems has received considerable interest [18], [19]. Excitability is also a critical property of biological spiking neurons [20], [21]. More recently, several excitable lasers have demonstrated biological-like spiking features.…”

Neuromorphic Computing with Memristor Crossbar

“…Figure (a) illustrates the complexity relationship between the data environment and machine. Although powerful software, efficient learning algorithms, and novel network topologies are emerging constantly, VCS‐based DNNs and SNNs still have drawbacks pertaining to the energy, area and time consumption . Therefore, the neuromorphic computing system (NCS) has been proposed for efficient implementation of neural networks.…”

The impact of Moore's Law and loss of Dennard scaling: Are DSP SoCs an energy efficient alternative to x86 SoCs?

“…The power constraints led to the concept of "dark silicon" [38], i.e., silicon that is underutilized. In todays' CPUs (22 nm technology) about 20% is dark [39], a percentage that is rapidly increasing as feature sizes keep being scaled down [40] such that by the end of the decade predictions range from 50% [39,41] to 90+% dark [38,40] silicon for processor dies. This fact poses interesting challenges and opportunities in processor design.…”