Data Acquisition System based on Subsampling Using Multiple Clocking Techniques

Oya, José R. García; Muñoz, F.; Torralba, A.; Jurado, Alejandro; Márquez, Francisco José Arenas; López-Morillo, E.

doi:10.1109/tim.2012.2200819

Cited by 10 publications

(23 citation statements)

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“…In order to reduce the folded noise effect, a method to improve the resolution has been proposed [8], employing two consecutive subsampling stages. The use of two subsampling processes allows the sampling frequency of the first stage to be increased, resulting in a lower contribution of the first S&H to the folded thermal noise [8]. Figure 11 shows two different alternatives for the implementation of a subsampling based receiver.…”

Section: Folded Thermal Noisementioning

confidence: 99%

“…Figure 11 shows two different alternatives for the implementation of a subsampling based receiver. Figure 11a illustrates the scheme for a unique subsampling process that was implemented in [7], while Figure 11b illustrates the scheme with two different clocks, as proposed by [8].…”

Section: Folded Thermal Noisementioning

confidence: 99%

“…Thus, there is no folding of N1 during the second sampling process. Therefore, the SNR improvement obtained with this sampling frequency plan is given by [8] …”

Section: Folded Thermal Noisementioning

confidence: 99%

“…In order to reduce the folded thermal noise effect, a new approach using two consecutives subsampling stages was implemented in [8]. The use of two subsampling processes allows the sampling frequency of the first stage to be increased, resulting in a lower contribution of the first S&H to the folded thermal noise.…”

Section: Multi-standard Receiver Based On Subsamplingmentioning

confidence: 99%

“…As a consequence, there is a tendency to design transceivers for multiple standards [1][2][3][4][5][6][7][8]. A similar problem arises in the test industry, where providers of testing and certification services to the wireless communication industry need multi-standard receivers, in order to reduce the cost in testing equipment.…”

Section: Introductionmentioning

confidence: 99%

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Subsampling Receivers with Applications to Software Defined Radio Systems

Oya¹,

Kwan²,

Chavero³

et al. 2012

Data Acquisition Applications

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Section: Folded Thermal Noisementioning

confidence: 99%

Section: Folded Thermal Noisementioning

confidence: 99%

“…Thus, there is no folding of N1 during the second sampling process. Therefore, the SNR improvement obtained with this sampling frequency plan is given by [8] …”

Section: Folded Thermal Noisementioning

confidence: 99%

Section: Multi-standard Receiver Based On Subsamplingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Subsampling Receivers with Applications to Software Defined Radio Systems

Oya¹,

Kwan²,

Chavero³

et al. 2012

Data Acquisition Applications

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A charge‐sharing analog‐to‐digital converter with embedded downconversion using a variable reference voltage

Pereira

Goes

2020

Circuit Theory & Apps

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SummaryIn the field of radio receivers, downconversion methods usually rely on one (or more) explicit mixing stage(s) before the analog‐to‐digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the converter's performance in terms of noise and linearity. As an alternative, we propose a receiver architecture that considers the ADC as both a quantizer and a downconverter block. This is achieved through the use of a variable reference signal (in this case, a voltage), as opposed to classic time‐invariant reference signals. When embedded into a charge‐sharing (CS) successive approximation register (SAR) ADC, this varying reference voltage is “saved” in the digital‐to‐analog converter (DAC) capacitor bank during the sampling phase, preventing any conversion errors. Furthermore, a phase‐locked loop (PLL) is used in order to provide an on‐chip solution for the generation of this variable reference voltage, which also removes the need for dedicated bandgap circuits and reference buffers. Post‐layout simulations of an 8‐bit 50 MS/s CS‐SAR ADC show that the proposed “embedded mixing” technique is able to downconvert a high‐frequency signal while also increasing the effective resolution by around 0.5 bits, when compared with a standard DC reference voltage.

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