Data acquisition system based on the Nios II for a CCD camera

Abstract

The FPGA with Avalon Bus architecture and Nios soft-core processor developed by Altera Corporation is an advanced embedded solution for control and interface systems. A CCD data acquisition system with an Ethernet terminal port based on the TCP/IP protocol is implemented in NAOC, which is composed of a piece of interface board with an Altera's FPGA, 32MB SDRAM and some other accessory devices integrated on it, and two packages of control software used in the Nios II embedded processor and the remote host PC respectively. The system is used to replace a 7200 series image acquisition card which is inserted in a control and data acquisition PC, and to download commands to an existing CCD camera and collect image data from the camera to the PC. The embedded chip in the system is a Cyclone FPGA with a configurable Nios II soft-core processor. Hardware structure of the system, configuration for the embedded soft-core processor, and peripherals of the processor in the PFGA are described. The C program run in the Nios II embedded system is built in the Nios II IDE kits and the C++ program used in the PC is developed in the Microsoft's Visual C++ environment. Some key techniques in design and implementation of the C and VC++ programs are presented, including the downloading of the camera commands, initialization of the camera, DMA control, TCP/IP communication and UDP data uploading.

Design and evaluation of a high-performance charge coupled device camera for astronomical imaging

“…This high-performance CCD camera is composed of three components: the CCD sensor module, the analogue system and the digital controller with an NIOS II soft-core embedded processor [5]. The analogue system includes a power and bias voltage circuit, a low noise amplifier, a 16 bit ADC, a power protection circuit and a CCD clock driver circuit.…”

“…The NIOS II processor system is equivalent to a microcontroller that includes an NIOS II IP core and a combination of peripherals and memory on a single chip. The NIOS II/'fast' core was selected for our system because it presents the most configuration options allowing us to fine-tune the processor's performance [5]. It is realized on an FPGA utilizing about 1600 LE resources.…”