Data Cache Prefetching Using a Global History Buffer

Last-Touch Correlated Data Streaming

“…For comparison with a larger L2, we quadruple the size of the L2 cache of the baseline processor to 4MB, conservatively assuming the same access latency as the base 1MB cache. We corroborate prior results [9,15] showing that GHB, an advanced stride/delta correlating predictor, can eliminate a large fraction of L2 cache misses in many applications, attaining on average 31% performance improvement across the applications we studied. Delta correlation is effective when the data layout is regular and accesses to distinct addresses follow a repeating pattern.…”

“…Table 3 compares LT-cords performance with the program counter / delta correlation variant of the Global History Buffer (GHB PC/DC, subsumes stride prefetching), a realistic DBCP implementation, and a baseline processor with a larger L2 cache. GHB uses 256-entry index and history tables, as recommended for SPEC applications [9,15]. The realistic DBCP is implemented with a 2MB on-chip correlation table as in [12].…”

“…More recently, researchers have proposed generalizing stride predictors to target miss sequences that exhibit recurring patterns of (non-constant) strides, an approach called delta correlation. The delta-correlating Global History Buffer (GHB) prefetcher [15] was recently shown t o out per f or m a var i ety of o th er har dwa re pr ef etch in g schemes [9]. Although delta correlation subsumes many previous approaches, it is not effective for data structures with irregular access patterns.…”

“…Another proposed class of prefetchers utilizes address correlation [3,4,10,11,15,20], which promises wider applicability across a diverse spectrum of workloads because they target generalized memory access patterns. Rather than detecting patterns in data layout, these prefetchers correlate data addresses to predict future misses.…”

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

“…Hardware and software prefetching techniques have been studied extensively [10,33,11,25,24,31,4]. Hardware-controlled prefetchers are highly effective for applications with regular data access patterns [4]; they have been integrated into all modern high-performance processors, including Intel Core i3/i5/i7, AMD Opteron and IBM POWER, and many embedded and mobile processors, such as ARM's Cortex-A9 and Cortex-A15.…”