Data dependent optimization of ROM structures

Abstract

Fig. 1. (a) Conventional ROM structure (b) NMOS static NOR row address decoder and (c) 3-bit column mux using pass transistors memory into multiple banks, with each bank having fewer data bits [11]. This would definitely improve the collapsibility of word lines. For example, a 32x16 ROM can be organized as 4 banks, each of 32x4. In this structure, only a maximum of 16 word lines need to be generated for each bank. Equations to compute transistor counts and advantages of the proposed structure over the conventional structure are discussed in the subsequent sections. III. TRANSISTOR COUNT ANALYSISThe following analysis is valid, as long as the conventional and the proposed ROM structures use the same circuit design style. The word line : ; ------0 Data word lines " . '--_.----• • ROM core •••• •••• A A (c) (b) A AddressAbstract-Read Only Memories (ROMs) occupy 40% to 80% of the area in most of the current generation System on Chips (SoCs ). Hence, any reduction in ROM area could effectively result in chips with low die area. A novel optimized ROM structure based on data contents is proposed in this paper. Customized address decoder and memory core are designed based on data contents leading to an area reduction of up-to 60 % and considerable reduction in power and access times. Analysis of overall transistor count is performed for a few real-life SoC applications and also for random data.