Data-flow based execution mechanisms of Parallel and Concurrent Prolog

Ito, Noriyoshi; Shimizu, Hajime; Kishi, Masasuke; Kuno, Eiji; Rokusawa, Kazuaki

doi:10.1007/bf03037114

Cited by 40 publications

(6 citation statements)

References 5 publications

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“…Another possible way is the parallel unification as in [7]. However, because the parallel unification needs the consistency checking overhead and the average numbe.r of arguments of literals is 2 or 3 [8], it seems that the parallel unification operation is not better than the sequential unification operation in general cases.…”

Section: Performancementioning

confidence: 99%

The architecture of the hardware unification unit and an implementation

Woo¹

1985

Proceedings of the 18th Annual Workshop on Microprogramming

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This paper describes the architecture and the current implementation of the hardware unification unit (HUU). The HUU performs the literal unification operation in Prolog processing. It is designed as a coprocessor to a host system that handles other operations of Prolog processing such as bookkeeping and sequencing. After the host system provides input values to the HUU and activates it, the HUU works independently from the host system; when it finishes its operation it reports the result to the host system. The HUU contains local memory that stores the variable binding information. The microinstructions and a sample microprogram of the HUU are described. Performance measures obtained from the HUU simulator are presented and discussed.

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Section: Performancementioning

confidence: 99%

The architecture of the hardware unification unit and an implementation

Woo¹

1985

Proceedings of the 18th Annual Workshop on Microprogramming

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“…If some or all of these subterms could be unified simultaneously each time a unification had to be performed, a large speedup could result. This approach includes the solution proposed in this thesis, along with the dataflow scheme used in the Japanese PIM-D machine [16] , and a technique for transforming some unifications to term matching, a problem that can be solved quickly in parallel [191. All of these other techniques will be addressed in chapter 8.…”

Section: Objectivesmentioning

confidence: 99%

Parallel Unification Scheduling in Prolog

Citrin¹,

Despain²

1986

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“…Several data flow models for execution of logic programs have been proposed. Ito et al [16] describe one such architecture for Parallel Prolog and Concurrent Prolog. The machine is designed to exploit AND, OR and unification parailelism.…”

Section: Previous Workmentioning

confidence: 99%

“…These units, however, do not perform parallel unificatio n with synchroni zation for shared variables. Special nodes for unificatio n have also been proposed for dataflow machines [16], where shared variables are handled by check consistenc y operators . We use a different approach to synchroni zation of shared variables, and our unificatio n units execute WAM based unificatio n instructio ns.…”

Section: The Unificati On Unitmentioning

confidence: 99%