Data forwarding in scalable shared-memory multiprocessors

Koufaty, David; Chen, Xiangfeng; Poulsen, David K.; Torrellas, Josep

doi:10.1109/71.553274

Cited by 46 publications

(26 citation statements)

References 19 publications

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“…Special deliver instruction initiates the sending of a cache block to processors specified by a bit vector. Koufaty et al proposed a framework for a compiler algorithm to insert data forwarding instructions in the code that exploits loop-level parallelism with do-all constructs [5]. Simulation analysis based on CC-UMA architecture has shown performance improvement of 50% for a system with large caches and 30% for a system with small caches.…”

Section: Related Workmentioning

confidence: 99%

“…This approach requires less sophisticated compiler support since it does not require identification of future consumers and it can be implemented at low cost. However, this approach is less flexible than classic data forwarding as defined in [5], because it does not allow forwarding to the processors not having the invalid copies of the data block.…”

Section: Introductionmentioning

confidence: 99%

“…For many programs and sharing patterns (e.g., producer-consumer), producer-initiated data transfers are a natural style of communication. Producer initiated primitives are known as data forwarding, delivery, remote writes, and software-controlled updates [5]. With data forwarding, when a processor produces the data (Fig 1c, processor P0), in addition to updating its cache, it sends a copy of the data to the caches of the processors that are identified by compiler or programmer as its future consumers.…”

Section: Introductionmentioning

confidence: 99%

“…Most of the studies [1,5,10,[13][14][15][16] examined the effectiveness of cache prefetching and data forwarding in CC-NUMA or CC-UMA architectures, except [18,19], which examined the potential of cache prefetching in bus-based multiprocessors. This study reported poor effectiveness of cache prefetching, despite assumed high memory latency.…”

Section: Introductionmentioning

confidence: 99%

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A performance evaluation of cache injection in bus-based shared memory multiprocessors

Milenkovic

Milutinović

2002

Microprocessors and Microsystems

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Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small-to medium-scale parallel machines today. In these systems the high memory latency poses the major hurdle in achieving high performance. One way to cope with this problem is to use various techniques for tolerating high memory latency. Software-controlled cache prefetching and data forwarding are two widely used techniques for tolerating high memory latency in scalable cache-coherent shared memory multiprocessors. However, some previous studies have shown that these techniques are not so effective in bus-based shared memory multiprocessors. In this paper, we propose a novel software-controlled technique called cache injection, which combines consumer and producer initiated approach, and broadcasting nature of bus. Performance evaluation based on program-driven simulation and a set of scientific applications and test benchmarks shows that cache injection is highly effective in reducing misses and bus traffic.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A performance evaluation of cache injection in bus-based shared memory multiprocessors

Milenkovic

Milutinović

2002

Microprocessors and Microsystems

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show abstract

“…While difficult to achieve in practice, it assumes that the last write self-invalidate [12,14] and ship the block to the reader through data forwarding. [1,2,10,12] that performs a timely delivery of data to the consumers. Under these assumptions, the coherence miss reduction using the CPC for a history depth of four is shown in Figure 10.…”

Section: Performance Potentialmentioning

confidence: 99%