Data memory design considering effective bitwidth for low-energy embedded systems

Cao, Yun; Tomiyama, Hiroyuki; Okuma, Takanori; Yasuura, Hiroto

doi:10.1145/581244.581245

Cited by 10 publications

(10 citation statements)

References 2 publications

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“…Infrequently accessed addresses are grouped into larger physical memory blocks. Later work by Cao et al [6] extends this optimization to consider data width scaling. Wuytack et al [16] have developed techniques to optimize the entire memory hierarchy of an application for power consumption based on application information.…”

Section: Related Workmentioning

confidence: 99%

Power-aware RAM mapping for FPGA embedded memory blocks

Tessier¹,

Betz²,

Neto³

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

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Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance.

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Section: Related Workmentioning

confidence: 99%

Power-aware RAM mapping for FPGA embedded memory blocks

Tessier¹,

Betz²,

Neto³

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

show abstract

“…While Section II-F discussed beneficial techniques, such as windowing for reducing the required memory, frequent access will still be required of this memory. Since accessing this memory dissipates energy [66], having an EC comparable to that of the datapath [50], it is desirable to minimize the number of memory accesses, in order to reduce the overall EC of an architecture.…”

Section: Memory Considerationsmentioning

confidence: 99%

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

Brejza

Maunder

et al. 2016

IEEE Commun. Surv. Tutorials

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Abstract-During the last two decades, wireless communication has been revolutionized by near-capacity Error-Correcting Codes (ECCs), such as Turbo Codes (TCs), which offer a lower Bit Error Ratio (BER) than their predecessors, without requiring an increased transmission Energy Consumption (EC). Hence, TCs have found widespread employment in spectrum-constrained wireless communication applications, such as cellular telephony, Wireless Local Area Network (WLAN) and broadcast systems. Recently however, TCs have also been considered for energyconstrained wireless communication applications, such as Wireless Sensor Networks (WSNs) and the 'Internet of Things' (IoT). In these applications, TCs may also be employed for reducing the required transmission EC, instead of improving the BER. However, TCs have relatively high computational complexities and hence the associated signal-processing-related ECs are not insignificant. Therefore, when parameterizing TCs for employment in energy-constrained applications, both the processing EC and the transmission EC must be jointly considered. In this tutorial, we investigate holistic design methodologies conceived for this purpose. We commence by introducing turbo coding in detail, highlighting the various parameters of TCs and characterizing their impact on the encoded bit rate, on the Radio Frequency (RF) bandwidth requirement, on the transmission EC and on the BER. Following this, energy-efficient TC decoder ApplicationSpecific Integrated Circuit (ASIC) architecture designs are exemplified and the processing EC is characterized as a function of the TC parameters. Finally, the TC parameters are selected in order to minimize the sum of the processing EC and the transmission EC.

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“…Memory Architecture Exploration is performed in [3] using a low-energy memory design method, referred as VAbM, that optimizes the memory area by allocating multiple memory banks with variable bit-width to optimally fit the application data. In [2], Benini et al, present a method that combines the memory allocation and data layout together to optimize the power consumption and area of memory architecture.…”

Section: A Related Workmentioning

confidence: 99%

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Kumar

Ravikumar

Govindarajan

2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

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Abstract-Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

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Data memory design considering effective bitwidth for low-energy embedded systems

Cited by 10 publications

References 2 publications

Power-aware RAM mapping for FPGA embedded memory blocks

Power-aware RAM mapping for FPGA embedded memory blocks

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

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