Data-oriented architecture for double and single bits error correction using Cycle Redundancy Code

Abstract

Error occurs during transferring, storing and retrieving data. Thus error detection and correction is a necessary technique in information technology. Cycle Redundancy Code, CRC, is a common method in error detection. A new method based on data-oriented theory for single and double bit errors correction by using CRC is presented. The conceptual model of presented method as data oriented architecture is designed to implement it with hardware. This method is able to determine the exact place of one and two bits in error and correct them. In a way, nonzero calculated remainder on receiver is compared with remainder field of the content of Problem Solution Data Structure, PSDS, to find the error location, as a solution.

Forward Backward Syndrome Computation: A Reduced Complexity CRC Code Decoder

“…When g(x) is irreducible over the set of polynomials with binary coefficients GF(2)[x], this hypothesis is fulfilled for N < 2 M . This method is called the table method [3]. Recently, in [5], another algorithm called "Table-Free Multiple Bit-Error Correction" (TFMBEC) Fig.…”

“…They are used to correct only single-bit errors or double-bit errors due to the exponential increase in complexity with the number of corrected errors. Similar to [3], [4], most methods are based on variations of the table method described in [1]. Recently, [5] proposed a "table-free method" using specific properties of the CRC code to decode one or two errors.…”