Data placement in HPC architectures with heterogeneous off-chip memory

Pavlovic, Milan; Puzovic, Nikola; Ramírez, Alex

doi:10.1109/iccd.2013.6657042

Cited by 16 publications

(12 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Using non-DRAM technologies or mixed DRAM technologies for main memory systems to improve power consumption on traditional CPUs has also been explored by several groups [4,9,28,34,[40][41][42]. Much of this work has focused on overcoming the performance peculiarities that future non-volatile memory (NVM) technologies may have compared to existing DRAM designs.…”

Section: Related Workmentioning

confidence: 98%

Page Placement Strategies for GPUs within Heterogeneous Memory Systems

Agarwal

Nellans

Stephenson

et al. 2015

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems

View full text Add to dashboard Cite

Systems from smartphones to supercomputers are increasingly heterogeneous, being composed of both CPUs and GPUs. To maximize cost and energy efficiency, these systems will increasingly use globally-addressable heterogeneous memory systems, making choices about memory page placement critical to performance. In this work we show that current page placement policies are not sufficient to maximize GPU performance in these heterogeneous memory systems. We propose two new page placement policies that improve GPU performance: one application agnostic and one using application profile information. Our application agnostic policy, bandwidth-aware (BW-AWARE) placement, maximizes GPU throughput by balancing page placement across the memories based on the aggregate memory bandwidth available in a system. Our simulation-based results show that BW-AWARE placement outperforms the existing Linux INTERLEAVE and LOCAL policies by 35% and 18% on average for GPU compute workloads. We build upon BW-AWARE placement by developing a compilerbased profiling mechanism that provides programmers with information about GPU application data structure access patterns. Combining this information with simple program-annotated hints about memory placement, our hint-based page placement approach performs within 90% of oracular page placement on average, largely mitigating the need for costly dynamic page tracking and migration.

show abstract

Section: Related Workmentioning

confidence: 98%

Page Placement Strategies for GPUs within Heterogeneous Memory Systems

Agarwal

Nellans

Stephenson

et al. 2015

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems

View full text Add to dashboard Cite

show abstract

“…Researchers have previously explored the use of data classification and intelligent data placement in hybrid memory systems, particularly in the context of HPC applications [7,24]. We apply this well-studied concept to large scale graph analytics applications and present our initial results that demonstrate the benefits of tiering with Graphmat.…”

Section: Related Workmentioning

confidence: 97%

Exploiting NVM in large-scale graph analytics

Malicevic

Dulloor

Sundaram

et al. 2015

Proceedings of the 3rd Workshop on Interactions of NVM/FLASH With Operating Systems and Workloads

View full text Add to dashboard Cite

Data center applications like graph analytics require servers with ever larger memory capacities. DRAM scaling, however, is not able to match the increasing demands for capacity. Emerging byte-addressable, non-volatile memory technologies (NVM) offer a more scalable alternative, with memory that is directly addressable to software, but at a higher latency and lower bandwidth.Using an NVM hardware emulator, we study the suitability of NVM in meeting the memory demands of four state of the art graph analytics frameworks, namely Graphlab, Galois, X-Stream and Graphmat. We evaluate their performance with popular algorithms (Pagerank, BFS, Triangle Counting and Collaborative filtering) by allocating memory exclusive from DRAM (DRAM-only) or emulated NVM (NVM-only).While all of these applications are sensitive to higher latency or lower bandwidth of NVM, resulting in performance degradation of up to 4⇥ with NVM-only (compared to DRAM-only), we show that the performance impact is somewhat mitigated in the frameworks that exploit CPU memory-level parallelism and hardware prefetchers.Further, we demonstrate that, in a hybrid memory system with NVM and DRAM, intelligent placement of application data based on their relative importance may help offset the overheads of the NVM-only solution in a cost-effective manner (i.e., using only a small amount of DRAM). Specifically, we show that, depending on the algorithm, Graphmat can achieve close to DRAM-only performance (within 1.2⇥) by

show abstract

“…To address the asymmetric performance and energy characteristics of NVM, pervious work explored the potential of carefully placing data on DRAM or NVM in hybrid memory system [27], comparing different policies for migrating data between the different modules [28], and finding data objects compatibility with the different modules by comparing different policies for migrating data between the different modules [29]. In contrast, we start by evaluating the potential of hybrid designs and ad-hoc placement policies assuming the existence of an oracle capable of statically partitioning the virtual address space, and at the same time we compare hybrid systems to a simpler hierarchical design that does not need partitioning policies.…”

Section: B Hybrid Memory Designmentioning

confidence: 99%

Evaluation of emerging memory technologies for HPC, data intensive applications

Suresh

Cicotti

Carrington

2014

2014 IEEE International Conference on Cluster Computing (CLUSTER)

View full text Add to dashboard Cite

DRAM technology has several shortcomings in terms of performance, energy efficiency and scaling. Several emerging memory technologies have the potential to compensate for the limitations of DRAM when replacing or complementing DRAM in the memory sub-system. In this paper, we evaluate the impact of emerging technologies on HPC and data-intensive workloads modeling a 5-level hybrid memory hierarchy design. Our results show that 1) an additional level of faster DRAM technology (i.e. EDRAM or HMC) interposed between the last level cache and DRAM can improve performance and energy efficiency, 2) a non-volatile main memory (i.e. PCM, STTRAM, or FeRAM) with a small DRAM acting as a cache can reduce the cost and energy consumption at large capacities, and 3) a combination of the two approaches, which essentially replaces the traditional DRAM with a small EDRAM or HMC cache between the last level cache and the non-volatile memory, can grant capacity and improved performance and energy efficiency. We also explore a hybrid DRAM-NVM design with a partitioned address space and find that this approach is marginally beneficial compared to the simpler 5-level design. Finally, we generalize our analysis and show the impact of emerging technologies for a range of latency and energy parameters.

show abstract

Data placement in HPC architectures with heterogeneous off-chip memory

Cited by 16 publications

References 18 publications

Page Placement Strategies for GPUs within Heterogeneous Memory Systems

Page Placement Strategies for GPUs within Heterogeneous Memory Systems

Exploiting NVM in large-scale graph analytics

Evaluation of emerging memory technologies for HPC, data intensive applications

Contact Info

Product

Resources

About