Data repair accelerating scheme for erasure-coded storage system based on FPGA and hierarchical parallel decoding structure

Symmetrical Data Recovery: FPGA-Based Multi-Dimensional Elastic Recovery Acceleration for Multiple Block Failures in Ceph Systems

“…However, current hardware acceleration schemes are mostly concentrated on theoretical and laboratory environment research [37][38][39], with relatively few application tests in real distributed storage system environments. This leads to specific problems and challenges that might arise in practical applications that have not been fully verified and resolved.…”

“…The timing strategy for data recovery when d 2 and c 1 data are corrupted is shown in Figure 7. This figure builds upon our team's previous work [39], ensuring performance while maximizing the frequency and efficiency of the FPGA design. Figure 7 describes the proposed timing optimization strategy in the case of losing two nodes and performing full node recovery in Cauchy RS (4,2).…”