Data retention reliability model of NROM nonvolatile memory products

Abstract

Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temperature. The functions are fitted to experimental results of products of three technology nodes. The retention loss is interpreted in terms of thermally activated lateral migration of trapped holes in the ONO layer. The holes' migration quenches the electrons' field over the channel of the device, degrading its threshold voltage. The migration process is presented as a dispersive transport process. Saturation of the retention loss is demonstrated at threshold voltage levels well above the neutral state of the device. From the retention loss function we derive a time-to-failure formula and an expression for the thermal acceleration factor of NROM products useful for determining stress conditions for accelerated reliability tests.

Investigation of Drain Disturb in SONOS Flash EEPROMs

“…Furthermore, repeated P/E cycling can also result in accumulation of trapped electrons above the channel region [23]. However, this cannot be significant for the present P/E conditions because of the good memory window observed during cycling (shown in the inset of Fig.…”

Comparison of local programming method for multi-bit/level 90nm SONOS memory

“…The programming charge distribution is identified by the charge pumping (CP) current [7] (I cp ) at one junction while the other junction is left floating.…”

Fundamental reliability issues of advanced charge-trapping Flash memory devices

“…Along the horizontal direction, clear evidences of the charge redistribution have been demonstrated in both NROM [8][9][10][11] and TANOS [12] devices. In NROM, charge injection mechanisms induce strongly localized charge distributions above the n-well [10], and two physically separated electron and hole distributions are present in the nitride layer after PIE operations, see Fig.…”

“…Their spatial mismatch generates a lateral dipole, whose electric field induces the lateral movement of both electrons and holes, thus explaining the V T shift occurring in retention [8,9]. Several experimental evidences have been proposed to support the lateral charge redistribution [11,12], despite experimental data relating the VT shift to the charge loss through the bottom oxide have been also reported [13]. The lateral charge redistribution has been shown to also be responsible of the VT reduction observed in TANOS devices [12].…”