Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth

Abstract

A mini-graph is a dataflow graph that has an arbitrary internal size and shape but the interface of a singleton instruction: two register inputs, one register output, a maximum of one memory operation, and a maximum of one (terminal) control transfer. Previous work has exploited dataflow sub-graphs whose execution latency can be reduced via programmable FPGA-style hardware. In this paper we show that mini-graphs can improve performance by amplifying the bandwidths of a superscalar processor's stages and the capacities of many of its structures without custom latency-reduction hardware. Amplification is achieved because the processor deals with a complete mini-graph via a single quasi-instruction, the handle. By constraining mini-graph structure and forcing handles to behave as much like singleton instructions as possible, the number and scope of the modifications over a conventional superscalar microarchitecture is kept to a minimum. This paper describes mini-graphs, a simple algorithm for extracting them from basic block frequency profiles, and a microarchitecture for exploiting them. Cycle-level simulation of several benchmark suites shows that minigraphs can provide average performance gains of 2-12% over an aggressive baseline, with peak gains exceeding 40%. Alternatively, they can compensate for substantial reductions in register file and scheduler size, and in pipeline bandwidth. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors

“…Other recent work [5,23] proposed CCA structures specifically optimized for linear chains of execution. That is to say these structures only execute subgraphs that have two inputs, one output, and a small number of intermediate nodes.…”

“…Other recent work [5] proposes using the DISE [9] framework to dynamically replace subgraphs in the instruction stream. A special instruction is used to signal the DISE engine, which then inserts the appropriate control logic into the pipeline.…”

Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping

“…Because of this drawback, many researchers have investigated accelerator designs that are more generalized. Some examples of these programmable computation accelerators include 3-1 ALUs [13,20], ALU pipelines [5], closed-loop ALUs [22], and function units [24].…”

“…Generally speaking, the main compilation challenge in generating code for accelerators is determining which portions of an application to execute on the accelerator and which portions to leave on the standard pipeline. Some researchers have looked into this problem before, proposing greedy algorithms [5,14], exact methods with exponential runtimes [16,17], or exact methods in conjunction with heuristics to avoid degenerate cases [10]. Here, previously proposed compiler algorithms are extended to take into account the reduced interconnect and the data-centric latency of the proposed accelerator design.…”

Scalable subgraph mapping for acyclic computation accelerators

“…Many DSPs have specialized hardware for common computations in signal and image processing, such as dot product, sum of absolute differences, and compare-select. A number of generalized accelerator designs have also been proposed, such as 3-1 ALUs [22,25], closed-loop ALUs [27], or ALU pipelines [5]. Larger accelerators can support bigger subgraphs and thus enhance the performance advantages.…”