Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Liu, Xinning; Chen, Mei; Cao, Peng; Zhu, Min; Shi, Longxing

doi:10.1587/transinf.e95.d.374

Cited by 16 publications

(16 citation statements)

References 24 publications

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“…MB row-level data parallelism reduces synchronization overhead, and this static mapping method greatly simplifies the scheduling problem. Compared to previous work [17], our method increase performance respectively more than 20% and 10% for I frame and P(B) frame.…”

Section: Mb Row-level Data Parallelismmentioning

confidence: 60%

“…REMUS-II, short for Reconfigurable Multimedia System 2, is a novel CGRA SoC that improves data-flow [17] and its corresponding control-flow compared with the previous version [18]. As shown in Fig.…”

Section: Remus-ii Architecture Overviewmentioning

confidence: 99%

“…To suit the data access pattern of multimedia applications, multiple data communication modes are supported. For more details, please refer to the paper [17].…”

Section: Remus-ii Architecture Overviewmentioning

confidence: 99%

“…6) can be implemented in the RPUs using either task pipeline or data parallelism. In our previous work [17], we have adopted a simple task pipelining method (Model1 in Fig. 7).…”

Section: Mb Row-level Data Parallelismmentioning

confidence: 99%

See 3 more Smart Citations

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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Section: Mb Row-level Data Parallelismmentioning

confidence: 60%

Section: Remus-ii Architecture Overviewmentioning

confidence: 99%

“…To suit the data access pattern of multimedia applications, multiple data communication modes are supported. For more details, please refer to the paper [17].…”

Section: Remus-ii Architecture Overviewmentioning

confidence: 99%

“…6) can be implemented in the RPUs using either task pipeline or data parallelism. In our previous work [17], we have adopted a simple task pipelining method (Model1 in Fig. 7).…”

Section: Mb Row-level Data Parallelismmentioning

confidence: 99%

See 2 more Smart Citations

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

Self Cite

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show abstract

“…), some adopt CGRA (e.g. MorphoSys [66], PACT XPP-III [67], ADRES [35], and REMUS [68] etc. ), while others incorporate both (e.g.…”

Section: Reconfigurable Processing Farbicsmentioning

confidence: 99%

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

Liu

Wang

Yin

et al. 2014

Sci. China Inf. Sci.

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Using the coarser operand grain and simplified interconnection patterns, CGRA (coarse grained reconfigurable architectures) has been proven to be energy efficient in several specific domains. As we know, the speed at which the contexts are applied to a PEA (processing element array) directly determines the performance of CGRA. In this paper, the design space in CGRA is further developed from the configuration granularity perspective by one middle-grained configuration granularity-the row-based configuration mechanism (RCM). The most prominent feature of the RCM is that a large DFG (data flow graph) can be mapped onto a small array in once reconfiguration, which is carried out on a row-by-row basis. Compared with an ordinary DFGpartitioning solution, the reconfiguration time and the data transfer time are well reduced. Furthermore, the proposed RCM offers much more efficient storage for the contexts. Compared with the DFG partitioning solution, the performance is boosted from 2.6% to 57.8%, while the area penalty is only 4.79% and the power penalty is only 7.22%. The RCM has been used in one reconfigurable processor called REMUS HPA (reconfigurable multi-media system, high performance version advanced). REMUS HPA has been implemented on a 50.5 mm 2 silicon with TSMC 65 nm technology. Simulation shows that 1920×1088@37 fps can be achieved for H.264 high-profile decoding when exploiting a 200 MHz working frequency. Compared with the high performance version of XPP (one commercial reconfigurable processor), the performance is 247% boosted.

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Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Cited by 16 publications

References 24 publications

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

A Survey on Reconfigurable System-on-Chips

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

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