DBT path selection for holistic memory efficiency and performance

Abstract

Dynamic binary translators (DBTs) provide powerful platforms for building dynamic program monitoring and adaptation tools. DBTs, however, have high memory demands because they cache translated code and auxiliary code to a software code cache and must also maintain data structures to support the code cache. The high memory demands make it difficult for memory-constrained embedded systems to take advantage of DBT-based tools. Previous research on DBT memory management focused on the translated code and auxiliary code only. However, we found that data structures are comparable to the code cache in size. We show that the translated code size, auxiliary code size and the data structure size interact in a complex manner, depending on the path selection (trace selection and link formation) strategy. Therefore, holistic memory efficiency (comprising translated code, auxiliary code and data structures) cannot be improved by focusing on the code cache only. In this paper, we use path selection for improving holistic memory efficiency which in turn impacts performance in memory-constrained environments. Although there has been previous research on path selection, such research only considered performance in memoryunconstrained environments.The challenge for holistic memory efficiency is that the path selection strategy results in complex interactions between the memory demand components. Also, individual aspects of path selection and the holistic memory efficiency may impact performance in complex ways. We explore these interactions to motivate path selection targeting holistic memory demand. We enumerate all the aspects involved in a path selection design and evaluate a comprehensive set of approaches for each aspect. Finally, we propose a path selection strategy that reduces memory demands by 20% and at the same time improves performance by 5-20% compared to an industrial-strength DBT.

Demand code paging for NAND flash in MMU-less embedded systems

“…This provides one word for every three instructions in the UCB to hold DBT data structures (i.e., mapping tables). The size of the mapping tables depends on the number of instructions in the UCB, and a 1:3 ratio is sufficient, particularly when data and code footprint reduction for DBT are applied [12], [6], [8], [5], [14]. Overall, the average speedups (bars "avg-all") are 1.02x with UCB-175% and 1.01x with UCB-75%.…”

“…Its size can be restricted to be smaller than the original binary size in flash. Thus, the code memory footprint can be made smaller with our demand-paging service than with full shadowing, and the savings in code footprint can be used to offset the relatively small data structures needed by DBT [6], [12]. Figure 3 illustrates the organization and management of the UCB.…”

“…DBT infrastructures have been ported to embedded platforms and research has been done to make their code and data structure memory usage small [12], [5], [6]. [14] explored using scratchpad memory (SPM) and main memory for the F$.…”

“…Due to these uses, it has also gained attention for embedded systems, with much research on memory and performance efficient DBT for embedded processors [4], [5], [6]. DBT has also been used to create embedded software services [7], [8].…”

Sptu

“…Meanwhile, there are also many other research works to improve the performance of DBT systems, such as code cache management [25], trace generation scheme [26,27], exit stub reduction [28], process-shared and persistent code cache [29,30], parallel optimizing on multi-core platforms [31]. Since these works does not focus on indirect branch handling, so we do not discuss the details here.…”