DC-DC converters: From discrete towards fully integrated CMOS

Steyaert, Michiel; Breussegem, Tom Van; Meyvaert, Hans; Callemeyn, Piet; Wens, Mike

doi:10.1109/esscirc.2011.6044912

Cited by 24 publications

(8 citation statements)

References 20 publications

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“…To regulate this noise, prior work proposed using explicit regulators with V-S PDN [4,10]. Considering the rapid improvement of capacitive technology, we focus on switching-capacitor (SC) converters in this paper, due to their regulation efficiency [11]. Fig.…”

Section: B Voltage Regulation In V-s Pdnmentioning

confidence: 99%

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Zhang

Mazumdar

Meyer

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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Ahstract-Aside from the benefits it brings, 3D-IC technology inevitably exacerbates the difficulty of power delivery with volumetrically increasing power consumption. Recent work managed to "recycle" current within the 3D stack by linking the different layers' supply/ground nets into a series connection. This charge-recycled (also known as voltage-stacked, or V-S) scheme provides a scalable so lution for 3D-IC's power delivery because it supports an arbitrary number of layers with a constant off-chip current demand. Although prior work has studied the circuit im plementation of a V-S power delivery network (PDN) and its current-reduction benefits, a whole-system evaluation of V-S PDNs' transient voltage noise and a noise comparison between the V-S PDN and the traditional PDN are miss ing. In this paper, we build a system-level model to exam ine voltage-stacked 3D-ICs' transient noise and explore the impact of different PDN design parameters and workload behaviors. Our results show that compared with the tra ditional PDN scheme, V-S provides stronger isolation for cross-layer noise interference, which in turn grants higher performance benefits for run-time noise mitigation tech niques, such as dynamic margin adaptation. We observe that, compared with traditional PDNs, V-S PDNs provide up to 60% lower transient noise in the worst-case scenario. Furthermore, we show that V-S PDNs significantly reduce the packaging cost, because their noise is almost insensitive to the package impedance (e.g., a 300% impedance increase only raises worst-case noise by less than 0.3% Vdd).

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Section: B Voltage Regulation In V-s Pdnmentioning

confidence: 99%

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Zhang

Mazumdar

Meyer

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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“…A positive EEF would result in e.g. increased autonomy for battery powered applications [23]. Although efficiency is lowest in the 5:1 converter mode, it is in this range that the highest improvement is seen over a linear regulator, which would barely achieve 15-18% power efficiency in this input voltage range.…”

Section: Measurement Resultsmentioning

confidence: 99%

Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter

Sarafianos

Steyaert

2015

IEEE J. Solid-State Circuits

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This paper presents a modified Dickson converter to achieve wide input range capacitive DC-DC converters. Several implementations are carefully studied and compared, which shows that the folding Dickson converter is the best choice, not only for its reduced dynamic losses, but also for its very regular structure and operation. Folding is achieved by merging the terminals of two or more flying capacitors, creating one equivalent flying capacitor. In this design, a four stage folding Dickson converter is implemented to achieve four different voltage conversion ratios. A Bootstrapped Gate Boost Converter (BGBC) is proposed which uses a bootstrapping technique to generate a floating rail for the flying switches, whose terminal voltages vary by large amounts depending on input voltage and VCR. The inherent operation of the Dickson topology is used by copying the voltage of the flying capacitors on a grounded capacitor in one phase, which can then be used to generate a floating 1.2 V in the second phase. The converter has been implemented in a 90 nm technology, achieving a maximum output power of 50 mW, peak efficiency of 76.6% in the 2:1 conversion mode, and an average efficiency above 60% over the entire Vin and Pout range. Index Terms-Dickson, folding, monolithic, SC-DCDC, switched capacitor, wide input-range.0018-9200

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“…Because of their energy-storage capability, these SC converters provide higher power-efficiency at the cost of a larger silicon area dedicated to the capacitors. Various surveys and comparisons of switching regulators in the literature [17] show that, with the rapid improvement of capacitive technology, switched-capacitors are going to surpass inductive converters. We therefore focus on SC converters in this paper and leave the study of inductive converters for future work.…”

Section: Voltage Regulation In V-s Pdnmentioning

confidence: 99%

“…Considering the fact that the fly-caps contribute to the majority of SC-converters' area and MIM capacitors have low density, we also calculate the converters' area overhead with other high-density integrated capacitors. For example, if imple- [17] or trench capacitors [12], the area of each converter would be 0.102mm 2 or 0.082mm 2 .…”

Section: Sc Converter Modelingmentioning

confidence: 99%

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC

Zhang

Mazumdar

Meyer

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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3D-IC technology brings both the opportunities to continue the historical trend of integration-level scaling and the challenges to deliver power reliably and efficiently. Voltagestacking (V-S), a charge-recycled power delivery scheme that connects the different layers' supply/ground nets into a series stack, provides a scalable solution to the 3D-IC power delivery wall. While prior work has extensively discussed the implementations of V-S at circuit-level, a cross-layer study that examines its system-level implications is missing. In this paper, we start with a circuit implementation of a charge-recycled voltage regulator and build an architecturelevel model to study the costs and benefits of utilizing V-S in 3D-IC. Our study shows that by significantly improving the EM-lifetime of C4 and TSV array (e.g., up to 5x) while only marginally increasing the average-case voltage noise (e.g., 0.75% Vdd IR drop), V-S provides a scalable solution for many-layer 3D-IC's power delivery challenge.

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DC-DC converters: From discrete towards fully integrated CMOS

Cited by 24 publications

References 20 publications

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC

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