2021 IEEE Applied Power Electronics Conference and Exposition (APEC) 2021
DOI: 10.1109/apec42165.2021.9487366
|View full text |Cite
|
Sign up to set email alerts
|

DC-Link Capacitor Current Modeling and Analysis for Three-Level Voltage Source Inverters

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1

Citation Types

0
3
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
4

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(3 citation statements)
references
References 15 publications
0
3
0
Order By: Relevance
“…Following the removal of the fault, the S switches and VSC are reset to DVR mode functioning. The DC link capacitance (Cdc) is designed using equation ( 2) [14][15].…”
Section: A Design Methodsmentioning
confidence: 99%
“…Following the removal of the fault, the S switches and VSC are reset to DVR mode functioning. The DC link capacitance (Cdc) is designed using equation ( 2) [14][15].…”
Section: A Design Methodsmentioning
confidence: 99%
“…The design tool in this paper derives the minimum DC-link capacitance values required during the converter design process. With the given system specifications and operating conditions, the DC-link capacitor currents of the 2L and 3L-NPC converters (i C of the 2L converter and i C1 /i C2 of the 3L-NPC converter in Figure 4) can be calculated analytically, as shown in ( 13) and ( 14), respectively [26,27]. Table 7 shows the detailed formulas for the parameters used in (14).…”
Section: Dc-link Voltage Current Ripple Calculationsmentioning
confidence: 99%
“…However, the ability of PWM methods to reduce NPP ripple varies based on power factor and modulation index. In [14], the authors analyse capacitor currents and state the analytical relationship between power factor, modulation index, and DC-link capacitor current. Jain et al [15] compare popular PWM methods in terms of their NPP ripple.…”
Section: Introductionmentioning
confidence: 99%