DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation

Rajput, Kapil K; Saini, Anil; Bose, S.

doi:10.1109/isvlsi.2010.46

Cited by 7 publications

(2 citation statements)

References 16 publications

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“…Overcoming this issue may result in a complex design [54]. Moreover, since subthreshold operation implies very low standby currents, the reduced transconductance leads to limited bandwidth (4a), which is only partially compensated by the lower MOS parasitic capacitances provided by the scaled technologies.…”

Section: Subthresholdmentioning

confidence: 99%

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

Grasso,

Pennisi,

Venezia

2023

Electronics

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This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors’ work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only “analog” approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area.

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Section: Subthresholdmentioning

confidence: 99%

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

Grasso,

Pennisi,

Venezia

2023

Electronics

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“…In order to have the specification of the IDAC, the estimated maximum dc-offset of the SAR baseband is simulated using Monte Carlo simulation. This method is used by a number of authors [5][6][7]. The statistic used in the simulation includes global variations and mismatch for local variations.…”

Section: Idac Main Specificationsmentioning

confidence: 99%

A 9-bit current-steering Digital to Analog Converter for differential dc-offset compensation of a baseband chain

Bakar

Murad

Ismail

et al. 2014

2014 IEEE Student Conference on Research and Development

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A current-steering Digital to Analog Converter (IDAC) to compensate dc-offset of a baseband chain in a Synthetic Aperture Radar (SAR) receiver is presented in this paper. The differential dc-offset can be injected with the current steer controlled by 9 digital control bits. The simulated LSB is 1.4 mV and the differential voltage range is 283 mV when it is connected to the baseband chain. This IDAC is implemented in a 130 nm CMOS technology and occupies 0.05 mm 2 of silicon area. From the postlayout simulation of the IDAC, the voltage range satisfies the specification obtained from the Monte Carlo simulations of the baseband chain. The 1 Least Significant Bit (1LSB) of the IDAC ensure the dc-offset at the input of the following ADC met the system requirement.

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Differential Structures

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Synthesis of Computational Structures for Analog Signal Processing

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DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation

Cited by 7 publications

References 16 publications

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

A 9-bit current-steering Digital to Analog Converter for differential dc-offset compensation of a baseband chain

Differential Structures

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