De-RISC: A Complete RISC-V Based Space-Grade Platform

Wessman, Nils-Johan; Malatesta, Fabio; Ribes, Stefano; Andersson, Jan; Garcia-Vilanova, Antonio; Masmano, Miguel; Nicolau, Vicente; Gomez, Paco; Rhun, Jimmy Le; Alcaide, Sergi; Cabo, Guillem; Bas, Francisco; Benedicte, Pedro; Mazzocchetti, Fabio; Abella, Jaume

doi:10.23919/date54114.2022.9774557

Cited by 9 publications

(6 citation statements)

References 5 publications

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“…However, some of the configurations are available only under a commercial license, such as the GRFPU to enable the high-performance FPU, or the FT-FPGA, which includes fault-tolerance features for either FPGA or ASIC implementations. In a multi-core configuration for high-performance accelerator under a research project [38], its performance is reportedly one of the highest in this work.…”

Section: Cpu Cores and Socsmentioning

confidence: 78%

A Survey on RISC-V-Based Machine Learning Ecosystem

et al. 2023

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In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and applications that have already reached a substantial growth, such as in natural language processing (NLP) and computer vision (CV). The developments of open-source hardware (OSH) and the contribution towards the creation of hardware-based accelerators with implication mainly in machine learning (ML), has also been significant. In particular, the reduced instruction-set computer-five (RISC-V) open standard architecture has been widely adopted by a community of researchers and commercial users, worldwide, in numerous openly available implementations. The selection through a plethora of RISC-V processor cores and the mix of architectures and configurations combined with the proliferation of ML software frameworks for ML workloads, is not trivial. In order to facilitate this process, this paper presents a survey focused on the assessment of the ecosystem that entails RISC-V based hardware for creating a classification of system-on-chip (SoC) and CPU cores, along with an inclusive arrangement of the latest released frameworks that have supported open hardware integration for ML applications. Moreover, part of this work is devoted to the challenges that are concerned, such as power efficiency and reliability, when designing and building application with OSH in the AI/ML domain. This study presents a quantitative taxonomy of RISC-V SoC and reveals the opportunities in future research in machine learning with RISC-V open-source hardware architectures.

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Section: Cpu Cores and Socsmentioning

confidence: 78%

A Survey on RISC-V-Based Machine Learning Ecosystem

et al. 2023

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“…In using this new ISA, the space industry can benefit not only from designing custom, reliable hardware for their purposes but also from the commercial environment. Companies developing dedicated hardware for space have also adopted this approach: Gaisler is developing the NOEL-V architecture [3], Microchip is leveraging SiFive's processor architectures for NASA's next High Performance Space Computing project [32], and dedicated projects like De-RISC [48] are pushing this development. In this work, we continue on this trend by exploiting an open-source industrially verified RISC-V core [18,22] as a building block for our system.…”

Section: Design Trends For Cps In Spacementioning

confidence: 99%

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Rogenmoser¹,

Tortorella²,

Rossi³

et al. 2023

Preprint

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Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation as well. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430 MHz, our fault-tolerant cluster achieves up to 1160 MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm 2 , representing a 1.3% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm 2 , namely ∼9.4% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the available redundant modes with minimum performance loss, allowing execution of a safety-critical portion of code with 310 and 23 clock cycles overhead for entry and exit, respectively. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs.

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“…The recent and explosive growth of the public and private aerospace domain has highlighted the inadequacies of current space-grade computing systems, which depend on outdated architectures with declining software ecosystems [1]. As an alternative to these older technologies, the RISC-V architecture comes as a major novelty to the open Instruction Architecture Set (ISA) domain, with a promising impact on the space sector that has been relying on open architectures for cost and customization reasons [1], [4], [17]. Thus, the RISC-V architecture appears to be a sensible alternative, with a maturing software ecosystem, extensive support from multiple domain organizations, and widespread adoption in the commercial and academic domains.…”

Section: Introductionmentioning

confidence: 99%

An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?

Forlin,

van Huffelen,

Cazzaniga

et al. 2023

2023 IEEE European Test Symposium (ETS)

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Fast development, low cost, and reconfigurability are becoming critical factors for aerospace applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in the user and on the configuration bits. For their correct functioning, they must be capable of withstanding failures without sacrificing much performance. When adjusting a soft core for these applications, it is essential to know where redundancies are necessary, to avoid unnecessary overhead. We characterize the reliability of an unprotected RISC-V microcontroller using an accelerated neutron beam. Our investigation shows that, for our chosen benchmark and processor, the user data in the memory banks is the leading cause of the total number of errors in the application. By reversing the benchmark operations, we could root cause the origin of the observed errors and found that most of the data corruption detected during the runs stem from previously corrupt input data or from output data that were corrupted while transmitting.

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De-RISC: A Complete RISC-V Based Space-Grade Platform

Cited by 9 publications

References 5 publications

A Survey on RISC-V-Based Machine Learning Ecosystem

A Survey on RISC-V-Based Machine Learning Ecosystem

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?

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