Deadlock-free XY-YX router for on-chip interconnection network

Jeong, Yeong Seob; Lee, Seung Eun

doi:10.1587/elex.10.20130699

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…By which particular logic is done by enabling input. Table 2 has description of the pins and by means of Mode_selection is intended to perform the chip's functions [18]. There are two at Mode_selection 1 data encryption logic and at 0 decryption logic [8].…”

Section: Device Utilization and Timingmentioning

confidence: 99%

Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm

Kumar¹,

Shyni²,

Peter³

et al. 2022

Wireless Communications and Mobile Computing

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In the technical world, NoC (network-on-chip) is a noticeable communication subsystem based on integrated circuits. It is mainly used in improving the performance of system-on-chip (SoC) by bridging the intellectual properties in the SoCs. But there is a need of protected architecture which is dealing with routing and processing data in the multicore system-on-chip (SoC). The recent issue with the above is there is still a drawback in enabling a better network routing system for accessing physical networks. The methodology of NoC mainly depends on the routing scheme, switching techniques, and structuring topologies. In this paper, we propose a new technique in implementing the chip in order to maintain the data privacy of NoC routers. There are many works with different algorithms that were evolved in enabling the secureness of NoCs, but due to the key size and block size, it is still not able to reach the expected effectiveness. Our proposed work is intended in designing a NoC architecture by means of embedding advanced TACIT security algorithm in Virtex-5 FPGA. Here, we used a hash function which is under a 4 hash function (4-H) scheme. The main advantage of this key generation scheme is it is applicable for block size and key size up to ‘ n ’ bit. Thus, this TACIT security algorithm enables ‘ n ’ bit using the software VHDL programming language in Xilinx ISE 14.2 and Modelsim 10.1 b which are applicable for 1024 bit and ‘ N ’ bits of block size on Virtex-5 FPGA systems. This design system can be enhanced by improving the factors like timing parameters, supporting memory, higher frequencies, and utilized summaries.

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Section: Device Utilization and Timingmentioning

confidence: 99%

Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm

Kumar¹,

Shyni²,

Peter³

et al. 2022

Wireless Communications and Mobile Computing

View full text Add to dashboard Cite

show abstract

“…(6) Crossed write: find previous write in other routers, then write the data to its linked data block and deliver data to output port in the DD stage, then bypass the data to other routers, then generate write updating orders in other To pass through the router network, we employ the meshed XY routing method, where the x-direction lines are endowed with high priority and y-direction lines are given low priority [12].…”

Section: Routing Pass and Network Topologymentioning

confidence: 99%

Filter router: An enhanced router design for efficient stacked shared cache network

Zhao

Jia

Watanabe

2019

IEICE Electron. Express

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In this paper, many shared cache accesses such as crossed accesses and repeated accesses will be filtered in proposed router network for purpose of access latency reduction. Firstly, the distribution features of all shared cache accesses are analyzed for further optimization on access latency. And then, a meshed router network integrated with enhanced routers is proposed for fast identification of target accesses and further handling them. Hence, the experimental results show that our network design can achieve an average improvement of 26.1 percent on speedup IPC and an average saving of 9.7 percent on energy consumption over base system.

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Design of a Deadlock-Free XY-YX Router for Network-on-Chip

Lee

Jeong

et al. 2016

Advances in Intelligent Systems and Computing

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Deadlock-free XY-YX router for on-chip interconnection network

Cited by 8 publications

References 4 publications

Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm

Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm

Filter router: An enhanced router design for efficient stacked shared cache network

Design of a Deadlock-Free XY-YX Router for Network-on-Chip

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