Debugging RTL Using Structural Dominance

Abstract

Abstract-RTL debug has become a resource-intensive bottleneck in modern VLSI CAD flows, consuming as much as 32% of the total verification effort. This work aims to advance the state-of-the-art in automated RTL debuggers, which return all potential bugs in the RTL, called solutions, along with corresponding corrections. First, an iterative algorithm is presented to compute the dominance relationships between RTL blocks. These relationships are leveraged to discover implied solutions with every new solution, thus significantly reducing the number of formal engine calls. Furthermore, a modern SAT solver is tailored to detect debugging non-solutions, sets of RTL blocks guaranteed to be bug-free, and imply other non-solutions using the precomputed RTL dominance relationships. Extensive experiments on industrial designs show a three-fold reduction in the number of SAT calls due to solution implications, coupled with faster SAT run-times due to non-solution implications, resulting in a 2.63x overall speed-up in total SAT solving time, demonstrating the robustness and practicality of the proposed approach.

Formal verification methodology for real‐time Field Programmable Gate Array

“…They also only perform functional verification and have not addressed timing verification. There are numerous formal approaches targeted at verification of RTL designs [15, 16]. However, these approaches do not address timing verification.…”