Decision-Directed Retention-Failure Recovery With Channel Update for MLC NAND Flash Memory

Aslam, Chaudhry Adnan; Guan, Yong Liang; Cai, Kui

doi:10.1109/tcsi.2017.2714902

Cited by 21 publications

(27 citation statements)

References 40 publications

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“…The MLC flash memory channel model in [11] is adopted here. According to [27]- [32], the read voltage of a 2-bit MLC NAND cell can be expressed by…”

Section: System Modelmentioning

confidence: 99%

“…The last one, n i , is cell-to-cell interference (CCI) caused by the voltage changing of neighbor cells, and it can be estimated and efficiently eliminated by pre-distortion [33], [34]. In summary, the cell threshold voltage of each state can be approximated using a Gaussian model [11], given by…”

Section: System Modelmentioning

confidence: 99%

“…4, one read operation needs N v reference voltages. Here N v is set to 6 to achieve a good balance between performance and reading cost [11]. The N v reference voltages in read operation are collected as v, i.e.,…”

Section: A Channel Updating Structurementioning

confidence: 99%

“…This method doesn't need extra memory sensing but requires the correctly decoded data which may be hard to collect under serious retention noise. Detector parameter estimation (DPE) [10] and RABP assisted channel update (RABP-CU) [11] are iteration based channel estimation methods, where they first constructed a cost function related to channel parameters, then got the estimation result by iteration optimizing algorithms such as gradient descent (GD). Although RABP-CU does not need extra sensing operations, it requires a large number of iterations to converge to a proper result, which leads to high complexity.…”

Section: Introductionmentioning

confidence: 99%

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A Discrete Detection and Decoding of MLC NAND Flash Memory With Retention Noise

Sun

Zheng

2020

IEEE Access

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The retention noise in MLC NAND flash memory has a great impact on reliability and lifetime of devices. How to recover information from the data corrupted by retention noise is a challenging problem. The joint processing of channel estimation, detection and low-density parity-check (LDPC) decoding is an effective method to handle this problem, while which is hindered by the limited computational resource of NAND flash memory devices. This paper proposes a discrete retention-failure recovery method, where the reading system only processes integers. The proposed method consists of two major components referred to binary tree searching (BTS) based channel updating and information bottleneck (IB) based LDPC decoding. In channel updating, the proposed learning based BTS algorithm can acquire reference voltages directly; thus it bypasses the intermediate stage of retention noise parameter estimation. The LDPC decoder is realized by IB based message passing, where node operation is achieved by lookup tables, and the messages passed between nodes are integers. Besides, a dynamic quantization level reduction strategy for IB based decoding is proposed to reduce the memory consumption of lookup tables. Finally, using PEG-constructed regular LDPC code (8000, 7200), the numerical results show that the proposed discrete method has much lower computational complexity and similar performance compared with the conventional method.

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“…The MLC flash memory channel model in [11] is adopted here. According to [27]- [32], the read voltage of a 2-bit MLC NAND cell can be expressed by…”

Section: System Modelmentioning

confidence: 99%

Section: System Modelmentioning

confidence: 99%

Section: A Channel Updating Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Discrete Detection and Decoding of MLC NAND Flash Memory With Retention Noise

Sun

Zheng

2020

IEEE Access

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“…In [20], cumulative distribution was estimated by either employing multiple sensing and decoding or interpolation with a bounded function. A retention-aware belief-propagation assisted channel update algorithm adjusted the input LLR of the second round decoding by estimating the mean and variance of the threshold voltage distribution under the assumption that the voltage distribution follows a Gaussian distribution [21]. Although these parametric-search-based schemes have attempted to estimate threshold voltage distribution and corresponding read reference voltages without knowledge of retention time, they rely on information acquired from multiple sensing and decoding, which results in excessive read latency.…”

Section: Introductionmentioning

confidence: 99%

Machine-Learning-Based Read Reference Voltage Estimation for NAND Flash Memory Systems Without Knowledge of Retention Time

et al. 2020

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To achieve a low error rate of NAND flash memory, reliable reference voltages should be updated based on the accurate knowledge of program/erase (P/E) cycles and retention time, because those severely distort the threshold voltage distribution of memory cell. Due to the sensitivity to the temperature, however, a flash memory controller is unable to acquire the exact knowledge of retention time, meaning that it is challenging to estimate accurate read reference voltages in practice. In this paper, we propose a novel machine-learning-based read reference voltage estimation framework for the NAND flash memory systems without the knowledge of retention time. To establish an unknown input-output relation of the estimation model, we derive input features by sensing and decoding memory cells in the minimum read unit. In order to define the relation between unlabeled input features and a pre-assigned class label, namely label read reference voltages, we propose three mapping functions: 1) k-nearest neighborsbased, 2) nearest-centroid-based, and 3) polynomial regression-based read reference voltage estimators. For the proposed estimation schemes, we analyze that the storage overhead and computational complexity are increasing function of the exploited feature dimension. Accordingly, we propose a feature selection (or dimension reduction) algorithm to select the minimum dimension and corresponding features to reduce the overhead and complexity while maintaining high estimation accuracy. Based on extensive numerical analysis, we validate that the derived features successfully replace unknown knowledge of retention time, and the proposed feature selection algorithm precisely adjusts the trade-off between overhead/complexity and estimation accuracy. Furthermore, the simulation and analysis results show that the proposed framework not only outperforms the conventional estimation schemes but also achieves the near-optimal frame error rate while sustaining low latency performance. INDEX TERMS NAND flash memory, read reference voltage estimation, machine learning, dimension reduction.

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