Deep-depletion high-frequency capacitance-voltage responses under photonic excitation and distribution of interface states in MOS capacitors

Kim, D.M.; Song, Seung Jin; Kim, H.T.; Kang, Dongyeon; Song, Sung-Hyuk; Min, Kyeong‐Sik

doi:10.1109/ted.2003.812096

Cited by 14 publications

(7 citation statements)

References 8 publications

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“…This is because HBTs operate with high current driving and this results in long-term degradation of interface states due to high temperature operation for high current operation. Sub-bandgap photonic technique reported in this work is similar to previously reported sub-bandgap photonic C-V characterization technique developed for MOS capacitors and the optical subthreshold current method for MOSFETs [8,9]. There are significant difference in the effect and characterization methods for interface states between unipolar devices and bipolar devices.…”

Section: Introductionsupporting

confidence: 68%

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Kim

Roh

Seo

et al. 2008

Microelectronics Reliability

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Section: Introductionsupporting

confidence: 68%

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Kim

Roh

Seo

et al. 2008

Microelectronics Reliability

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“…We have shown previously that photo-illumination of the MOS structure can generate a higher number of minority carriers [3], which enable them to interact with these deep level states, allowing their characterization. In this work, we have extended the analysis to include sub-bandgap illumination to investigate the decay time of deep level traps [4] without the influence of minority carriers. stack is used to increase the critical electric field in the device.…”

Section: Introductionmentioning

confidence: 99%

Identification of Slow States at the SiO<sub>2</sub>/SiC Interface through Sub-Bandgap Illumination

Spargo

Furnival

Mahapatra

et al. 2012

MSF

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We show that it is possible to obtain information relating to deep level interface traps, or so called ‘slow states’, by using the photo-CV characterisation method. Sub-bandgap illumination has been chosen in order to avoid band-to-band excitation for the creation of minority carriers. This enables information to be extracted from trapping states at the SiO2/SiC interface that are energetically deep within the band gap. Empirical observations of deep level trapping states with life times in the order of tens of hours are reported and the interface trap density as a function of energy has been extracted using the Terman method. Characterisation of these interface states will aid the development of new fabrication processes, with the aim of reducing the interface trap density to the same level as that of the SiO2/Si interface and facilitating the production of higher quality SiC based devices.

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“…[5][6][7] The C-V DD behavior in p-type substrates can be induced due to the lack of minority carriers since the tunneling of minority carriers from substrate through ultra thin oxide is large, and therefore the depletion width (W D ) will be expanded continually. [8][9][10][11] When the DD occurs, tunneling current becomes saturated because of the slow generation rate of carriers in the substrate. 12 In addition, it was reported that the minority carrier tunneling increases with the doping concentration, i.e., the DD behavior was easily induced in a heavily doped MOS device.…”

mentioning

confidence: 99%

Non-Planar Substrate Metal-Oxide-Semiconductor Photo-Capacitance Detectors with Enhanced Deep Depletion Sensitivity at Convex Corner

Tseng

Hwu

2014

ECS J. Solid State Sci. Technol.

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Non-planar substrate metal-oxide-semiconductor (MOS) photo-capacitance detector with enhanced deep depletion (DD) at convex corner was demonstrated. The expansion-shrinkage mechanism of depletion width due to illumination was adopted. For non-planar substrate MOS devices, the enhanced photo-capacitance sensitivity in deep depletion region is caused by the large variation of depletion width at convex corners. The smaller area device shows lager photo-capacitance sensitivity due to the shorter distance between the edge of illumination and the convex corner. The significant enhanced photo-capacitance variation sensitivity (ΔC/C) of 85.5% was achieved for non-planar MOS device with an EOT of 2.8 nm in the smallest area of 160 × 160 μm2 which respect to that of 7% for planar one under the same illumination intensity of 90 mW/cm2.

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Deep-depletion high-frequency capacitance-voltage responses under photonic excitation and distribution of interface states in MOS capacitors

Cited by 14 publications

References 8 publications

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Identification of Slow States at the SiO<sub>2</sub>/SiC Interface through Sub-Bandgap Illumination

Non-Planar Substrate Metal-Oxide-Semiconductor Photo-Capacitance Detectors with Enhanced Deep Depletion Sensitivity at Convex Corner

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