Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm

Negi, Kazuhiro; Dohi, Keisuke; Shibata, Yuichiro; Oguri, Kazuta

doi:10.1109/fpt.2011.6132679

Cited by 77 publications

(51 citation statements)

References 11 publications

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“…As reported in [35], [36] and [38], a pre-calculated table provides a cheaper (in terms of hardware usage level) alternative. They directly quantize the pixels angular value from its corresponding gradients.…”

Section: Integer Arithmeticsmentioning

confidence: 99%

“…Integer hardware gradient extraction is well-known in literature, as described in [35], [36], [37], [38], [39] and [40]. Those solutions present a fully custom and dedicated hardware for spatial gradient extraction.…”

Section: Integer Arithmeticsmentioning

confidence: 99%

“…As proposed by [38], the corner domain is sampled in N bins, called Θ k . The angle resolution is then Each versorî k can be defined as:…”

Section: Our Proposalmentioning

confidence: 99%

See 2 more Smart Citations

Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

Maggiani¹,

Salvadori²,

Petracca³

et al. 2013

2013 Seventh International Conference on Distributed Smart Cameras (ICDSC)

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Smart Camera Networks (SCNs) is nowadays an emerging research field which represents the natural evolution of centralized computer vision applications towards full distributed and pervasive systems. In this vision, one of the biggest effort is in the definition of a flexible and reconfigurable SCN node architecture able to remotely update the application parameter and the performed computer vision application at runtime. In this respect, we present a novel SCN node architecture based on a device in which a microcontroller manage all the network functionality as well as the remote configuration, while an FPGA implements all the necessary module of a full computer vision pipeline. In this work the envisioned architecture is first detailed in general terms, then a real implementation is presented to show the feasibility and the benefits of the proposed solution. Finally, performance evaluation results underline the potential of an hardware software codesign approach in reaching flexibility and reduced processing time.

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Section: Integer Arithmeticsmentioning

confidence: 99%

Section: Integer Arithmeticsmentioning

confidence: 99%

See 1 more Smart Citation

Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

Maggiani¹,

Salvadori²,

Petracca³

et al. 2013

2013 Seventh International Conference on Distributed Smart Cameras (ICDSC)

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show abstract

“…Their architecture can process 640 × 480 image at 30 FPS with operating frequency 127.49 MHz on Stratix II FPGA, but detection part is not implemented. After we presented a preliminary version of this paper [1], Komorkiewicz et al [12] presented fullypipelined HOG and SVM implementation without using any external memory. To achieve superior accuracy, they used single-precision floating-point arithmetic for all stages of processing on a Virtex-6 XC6VLX240T FPGA.…”

Section: Introductionmentioning

confidence: 99%

“…* A preliminary version of this paper appeared in the Proceedings of the 2011 International Conference on Field-Programmable Technology, New Delhi, India, December 12-14, 2011 [1].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Human Detection by HOG Features with AdaBoost

Dohi

Negi

Shibata

et al. 2013

IEICE Trans. Inf. & Syst.

Self Cite

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SUMMARYWe implement external memory-free deep pipelined FPGA implementation including HOG feature extraction and AdaBoost classification. To construct our design by compact FPGA, we introduce some simplifications of the algorithm and aggressive use of stream oriented architectures. We present comparison results between our simplified fixed-point scheme and an original floating-point scheme in terms of quality of results, and the results suggest the negative impact of the simplified scheme for hardware implementation is limited. We empirically show that, our system is able to detect human from 640 × 480 VGA images at up to 112 FPS on a Xilinx Virtex-5 XC5VLX50 FPGA.

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Adaptive human detection approach using FPGA‐based parallel architecture in reconfigurable hardware

Gai

Qiu

et al. 2016

Concurrency and Computation

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Summary Currently, the rapid increment of human detections has been changing people's daily life, However, the implementation is still facing the challenges caused by the restrictions of power and hardware. The computation process results in a heavy workload even though prior researches had made efforts to reduce the complexity. We focus on this issue and propose a new approach that employs the binarization‐based optimization algorithm to simplify the computation processes. Our approach is designed to minimize the necessary calculations and memory space. Moreover, we have developed the field‐programmable gate array‐based parallel architecture to apply partial dynamic reconfiguration, which enables the remote configurations for the number of processing units. An experimental evaluation is completed in order to examine our proposed approach. According to our experimental results, the detection precision can reach a miss rate less than 1.97% and a false positive rate of 1%. The energy cost is also reduced up to 36% comparing with the prior methods. Copyright © 2016 John Wiley & Sons, Ltd.

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Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm

Cited by 77 publications

References 11 publications

Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

FPGA Implementation of Human Detection by HOG Features with AdaBoost

Adaptive human detection approach using FPGA‐based parallel architecture in reconfigurable hardware

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