Deep sub-0.1-�m MOSFETs with very thin SOI layer for ultralow-power applications

Takamiya, Makoto; Yasuda, Yasuhiko; Hiramoto, Toshiro

doi:10.1002/(sici)1520-6432(199811)81:11<18::aid-ecjb3>3.0.co;2-m

Cited by 1 publication

(1 citation statement)

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“…It is well acknowledged that the main advantage of the fully depleted SOI (FD-SOI) MOSFET when compared with other technologies is the steep sub-threshold swing. However, the value of the swing tends to increase with the reduction of gate length, which can be controlled by key parameters such as thickness of the active SOI layer [32], reducing the thickness of the buried-oxide [33] and by fabricating a buried layer [34]. Most of the above-mentioned technology enhancement techniques have been implemented in the devices highlighted in figure 4.…”

Section: Sub-threshold Swingmentioning

confidence: 99%

Review on analog/radio frequency performance of advanced silicon MOSFETs

Passi

Raskin

2017

Semicond. Sci. Technol.

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Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of draininduced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore's law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.Keywords: analog and radio-frequency figures of merit, digital figures of merit, multiple gate field effect transistor, ultra-thin body buried-oxide, III-V and two-dimensional channel field effect transistor

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Section: Sub-threshold Swingmentioning

confidence: 99%